Compaq ECQD2KCTE manual Index-10

with, 4–138

Pixel error instruction, 4–154

PKLB (Pack longwords to bytes) instruction, 4–155PKWB (Pack words to bytes) instruction, 4–155Prefetch data (FETCH instruction), 4–139PRIORITY_ENCODE operator, 3–9

Privileged Architecture Library. See PALcode Processor communication, 5–15

Processor cycle counter (PCC) register, 3–3RPCC instruction with, 4–143

Processor issue constraints, 5–12Processor issue sequence, 5–12Processor type assignments, D–1

Program counter (PC) register, 3–1with EXCB instruction, 4–138

Pseudo-ops,A–14

Q

Quadword data type, 2–2

alignment of, 2–3 ,2–12atomic access of, 5–2

integer floating-point format, 2–12T_floating with, 2–12

R

R31

restrictions, 3–1RAZ (read as zero), 1–9

RC (read and clear) instruction, 4–150

RDUNIQUE (PALcode) instruction required recognition of, 6–4

Read/write ordering (multiprocessor), 5–10

determining requirements, 5–10hardware implications for, 5–29memory location defined, 5–11

Read/write, sequential, A–8

Regions in physical address space, 5–1

Registers, 3–1

floating-point,3–2integer, 3–1lock, 3–2

memory prefetch, 3–3optional, 3–3

processor cycle counter, 3–3program counter (PC), 3–1value when unused, 3–10VAX compatibility, 3–3 See also specific registers

Register-to-register move, A–13

Relational Operators, 3–9

Representative result, 4–64

Reserved instructions, opcodes for, C–21Result latency, A–4

RET instruction, 4–22

RIGHT_SHIFT(x,y) operator, 3–9

Rounding modes. See Floating-point rounding modes

RPCC (read processor cycle counter) instruction, 4–143

RS (read and set) instruction, 4–150

S

S_floating data type

alignment of, 2–8compared to F_floating, 2–8exceptions, 2–8mapping, 2–7MAX/MIN, 4–65

NaN with T_floating convert, 4–88operations, 4–62

S4ADDL instruction, 4–26S4ADDQ instruction, 4–28S4SUBL instruction, 4–38S4SUBQ instruction, 4–40S8ADDL instruction, 4–26S8ADDQ instruction, 4–28S8SUBL instruction, 4–38S8SUBQ instruction, 4–40SBZ (should be zero), 1–9

Security holes, 1–7

with UNPREDICTABLE results, 1–8Sequential read/write, A–8Serialization, MB instruction with, 4–142SEXT(x) operator, 3–9

Shared data (multiprocessor), A–5changed vs. updated datum, 5–6

Shared data structures

atomic update, 5–7

ordering considerations, 5–9

using memory barrier (MB) instruction, 5–9Shared memory

accessing, 5–11defined, 5–10

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