there is at least one byte that is accessed by both, that is, if max(x,y) < min(x+m,y+n).
5.6.1.1 Architectural Definition of Processor Issue Sequence
The issue sequence for a processor is architecturally defined with respect to a hypothetical sim- ple implementation that contains one processor and a single shared memory, with no caches or buffers. This is the instruction execution model:
1.
2.Read/Write: That instruction is executed and runs to completion, including a single data read from memory for a Load instruction or a single data write to memory for a Store instruction.
3.Update: The PC for the processor is updated.
4.Loop: Repeat the above sequence indefinitely.
If the instruction fetch step gets a memory management fault, the
5.6.1.2 Definition of Before and After
The ordering relation BEFORE (⇐ ) is a partial order on memory accesses. It is further defined in Sections 5.6.1.3 through 5.6.1.9.
The ordering relation BEFORE (⇐ ), being a partial order, is acyclic.
The BEFORE order cannot be observed directly, nor fully predicted before an actual execu- tion, nor reproduced exactly from one execution to another. Nonetheless, some useful ordering properties must hold in all Alpha implementations.
If u ⇐ v, then v is said to be AFTER u.
5.6.1.3 Definition of Processor Issue Constraints
Processor issue constraints are imposed on the processor issue sequence defined in Section 5.6.1.1, as shown in Table
