System Architecture and Programming Implications | Compaq ECQD2KCTE

5	System Architecture and Programming Implications
	5.1	Introduction	5–1
	5.2	Physical Address Space Characteristics	5–1
	5.2.1	Coherency of Memory Access	5–1
	5.2.2	Granularity of Memory Access	5–2
	5.2.3	Width of Memory Access	5–3
	5.2.4	Memory-Like and Non-Memory-Like Behavior	5–3
	5.3	Translation Buffers and Virtual Caches	5–4
	5.4	Caches and Write Buffers	5–4
	5.5	Data Sharing	5–6
	5.5.1	Atomic Change of a Single Datum	5–6
	5.5.2	Atomic Update of a Single Datum	5–6
	5.5.3	Atomic Update of Data Structures	5–7
	5.5.4	Ordering Considerations for Shared Data Structures	5–9
	5.6	Read/Write Ordering	5–10
	5.6.1	Alpha Shared Memory Model	5–10
	5.6.1.1	Architectural Definition of Processor Issue Sequence	5–12
	5.6.1.2	Definition of Before and After	5–12
	5.6.1.3	Definition of Processor Issue Constraints	5–12
	5.6.1.4	Definition of Location Access Constraints	5–14
	5.6.1.5	Definition of Visibility	5–14
	5.6.1.6	Definition of Storage	5–14
	5.6.1.7	Definition of Dependence Constraint	5–15
	5.6.1.8	Definition of Load-Locked and Store-Conditional	5–16
	5.6.1.9	Timeliness	5–17
	5.6.2	Litmus Tests	5–17
	5.6.2.1	Litmus Test 1 (Impossible Sequence)	5–17
	5.6.2.2	Litmus Test 2 (Impossible Sequence)	5–18
	5.6.2.3	Litmus Test 3 (Impossible Sequence)	5–18
	5.6.2.4	Litmus Test 4 (Sequence Okay)	5–19
	5.6.2.5	Litmus Test 5 (Sequence Okay)	5–19
	5.6.2.6	Litmus Test 6 (Sequence Okay)	5–19
	5.6.2.7	Litmus Test 7 (Impossible Sequence)	5–20
	5.6.2.8	Litmus Test 8 (Impossible Sequence)	5–20
	5.6.2.9	Litmus Test 9 (Impossible Sequence)	5–21
	5.6.2.10	Litmus Test 10 (Sequence Okay)	5–21
	5.6.2.11	Litmus Test 11 (Impossible Sequence)	5–21
	5.6.3	Implied Barriers	5–22
	5.6.4	Implications for Software	5–22
	5.6.4.1	Single Processor Data Stream	5–22
	5.6.4.2	Single Processor Instruction Stream	5–22
	5.6.4.3	Multiprocessor Data Stream (Including Single Processor with DMA I/O)	5–22
	5.6.4.4	Multiprocessor Instruction Stream (Including Single Processor with DMA I/O) . . .	5–23
	5.6.4.5	Multiprocessor Context Switch	5–24
	5.6.4.6	Multiprocessor Send/Receive Interrupt	5–26
	5.6.4.7	Implications for Memory Mapped I/O	5–27
	5.6.4.8	Multiple Processors Writing to a Single I/O Device	5–28
	5.6.5	Implications for Hardware	5–29
	5.7	Arithmetic Traps	5–30

6 Common PALcode Architecture

6.1	PALcode	6–1
6.2	PALcode Instructions and Functions	6–1
6.3	PALcode Environment	6–2
6.4	Special Functions Required for PALcode	6–2

vii

Image 7

Compaq ECQD2KCTE manual System Architecture and Programming Implications

Contents

Alpha Architecture Handbook October Table of Contents Instruction Formats Page 10.19 Integer Register to Floating-Point Register Move System Architecture and Programming Implications Digital Unix Ieee Floating-Point Conformance Index Figures Tables Xiii Xiv Preface Page Alpha Is Designed for Very High-Speed Implementations ChapterAlpha Approach to Risc Architecture Alpha Is a True 64-Bit Architecture PALcode Alpha’s Very Flexible Privileged Software Library Alpha Approach to Byte ManipulationAlpha Approach to Multiprocessor Shared Memory Alpha Instructions Include Hints for Achieving Higher Speed Alpha and Programming Languages Data Format Overview Instruction Overview Instruction Format OverviewPALcode Instructions Load/Store Instructions Branch InstructionsInteger Operate Instructions Terminology and Conventions Instruction Set CharacteristicsFloating-Point Operate Instructions Security Holes NumberingUnpredictable and Undefined Aligned and Unaligned Ranges and ExtentsUnaligned Ignore IGN Must Be Zero MBZRead As Zero RAZ Should Be Zero SBZPage Word AddressingData Types Byte Quadword Longword Ffloating VAX Floating-Point Formats Gfloating Ffloating Load Exponent Mapping Mapf Dfloating Gfloating Register Format Ieee Floating-Point Formats Sfloating Load Exponent Mapping Maps Memory Register SFloating 13 Tfloating Datum Tfloating XFloating 14 Tfloating Register Format XFloating Big-Endian Formats 15 Xfloating Datum 17 Xfloating Big-Endian Datum Longword Integer Format in Floating-Point Unit Data Types with No Hardware Support Quadword Integer Format in Floating-Point Unit 23 Little-Endian Byte Addressing Big-Endian Addressing Support 14Alpha Architecture Handbook Implementation note Alpha RegistersProgram Counter Integer Registers Lock Registers Floating-Point Registers Memory Prefetch Registers NotationProcessor Cycle Counter PCC Register Optional Registers Expression Operand Notation Meaning Operand NotationOperand Notation Meaning Operand Value Notation Meaning Operand Name Notation Operand Access Type NotationOperand Access Type Notation Meaning Instruction Operand Notation Operators Meaning OperatorsOperand Data Type Notation Operand Data Type Notation Meaning Bit concatenation DIV CaseLoadlocked LTU NotPhysicaladdress Priorityencode XOR Instruction FormatsNotation Conventions Software Note Memory Format Instructions with a Function Code Memory Instruction Format Operate Instruction Format Branch Instruction FormatMemory Format Jump Instructions Floating-Point Operate Instruction Format Floating-Point Operate Instruction Format Floating-Point Convert Instructions PALcode Instruction FormatFloating-Point/Integer Register Moves PALcode Instruction Format Page Instruction Type Section Instruction Set Overview Floating-Point Subsets Subsetting Rules Opcode Qualifiers Software Emulation RulesOpcode Qualifiers Meaning Memory Integer Load/Store Instructions Mnemonic Operation Memory Integer Load/Store Instructions Load Address LDL Load Memory Data into Integer Register Implementation Notes Load Unaligned Memory Data into Integer Register Load Memory Data into Integer Register Locked 10Alpha Architecture Handbook Implementation Notes Store Integer Register Data into Memory Conditional Stqc BEQ Hardware/Software Implementation Note Store Integer Register Data into Memory 16Alpha Architecture Handbook Store Unaligned Integer Register Data into Memory Control Instructions Summary Mnemonic Operation Control Instructions JSR BNEBSR JMP Conditional Branch Unconditional Branch Jumps Encoding Meaning Count instruction CIX extension implementation note Integer Arithmetic InstructionsInteger Arithmetic Instructions Summary Mnemonic Operation Addl Longword Add S4ADDL Scaled Longword AddS8ADDL Addq Quadword Add S4ADDQ Scaled Quadword AddS8ADDQ Integer Signed Compare Integer Unsigned Compare Count Leading Zero Count Population Count Trailing Zero Mull Longword Multiply Mulq Quadword Multiply Unsigned Quadword Multiply High Subl Longword Subtract S4SUBL Scaled Longword SubtractS8SUBL Subq Quadword Subtract S4SUBQ Scaled Quadword SubtractS8SUBQ Logical and Shift Instructions Summary Mnemonic Operation Logical and Shift Instructions Logical Functions Conditional Move Integer Is exactly equivalent to Shift Logical Shift Arithmetic Instruction Meaning Described in Section Byte Manipulation Instructions Mskbl InswhInslh Insqh BEQ Loop Compare Byte To compare two character strings for greater/equal/less Extract Byte Ldqu Optimized examples Big-endian examples Byte Insert 56Alpha Architecture Handbook Byte Mask Insqh Inswh Sign Extend Zero Bytes Floating-Point Instructions Subsets and FaultsSingle-Precision Operations Alpha finite number Definitions Non-finite number DenormalDirty zero Infinity Meaning Finite EncodingsTrue zero Sign Exponent Fraction Vax VAX Rounding Modes Rounding ModesIeee Rounding Modes VAX-Format Arithmetic with Precise Exceptions VAX Rounding Mode Instruction NotationIeee Rounding Mode Instruction Notation Computational Models IEEE-Compliant Arithmetic High-Performance VAX-Format ArithmeticIEEE-Compliant Arithmetic Without Inexact Exception High-Performance IEEE-Format Arithmetic Trapping ModesVAX Trapping Modes When /U or /V mode is specified Ieee Trapping Modes VAX Trapping Modes Summary Trap Mode Notation Meaning SUI Summary of Ieee Trapping Modes Trap Mode Notation Meaning SVI Arithmetic Trap Completion Trap Shadow Length Rules Page Invalid Operation INV Arithmetic Trap Overflow OVF Arithmetic Trap Division by Zero DZE Arithmetic Trap Integer Overflow IOV Arithmetic Trap Ieee Floating-Point Trap Disable BitsUnderflow UNF Arithmetic Trap Inexact Result INE Arithmetic Trap Ieee Denormal Control Bits Floating-Point Control Register Fpcr Floating-Point Control Register Fpcr Format Ieee Rounding Mode SelectedPage Accessing the Fpcr Saving and Restoring the Fpcr Default Values of the FpcrSoftware Notes Floating-Point Instruction Function Field Floating-Point Instruction Function Field Format Contents Meaning for Opcodes 1616 ITOFS/ITOFT FNCSQRTS/SQRTT Unpredictable Conversion of NaN and Infinity Values Ieee Standard Generating NaN Values Copying NaN ValuesPropagating NaN Values Memory Format Floating-Point Instructions Load Ffloating Load Gfloating Load Sfloating Load Tfloating Store Ffloating Store Gfloating Store Sfloating Store Tfloating Branch Format Floating-Point Instructions FBxx Fa.rq,disp.al Branch format Page Floating-Point Operate Format Instructions Ieee AddfAddg Adds Mult MulfMulg Muls Copy Sign Convert Integer to Integer Floating-Point Conditional Move Fcmovne F3,F2,F1 Move from/to Floating-Point Control Register VAX Floating Add Ieee Floating Add Cmpglt VAX Floating CompareCmpgeq Cmpgle Cmptlt Ieee Floating CompareCmpteq Cmptle Convert VAX Floating to Integer Convert Integer to VAX Floating Convert VAX Floating to VAX Floating Convert Ieee Floating to Integer Convert Integer to Ieee Floating Convert Ieee SFloating to Ieee TFloating Convert Ieee TFloating to Ieee SFloating VAX Floating Divide Ieee Floating Divide Floating-Point Register to Integer Register Move Integer Register to Floating-Point Register Move Itofs is exactly equivalent to the sequence VAX Floating Multiply Ieee Floating Multiply VAX Floating Square Root Ieee Floating Square Root VAX Floating Subtract Ieee Floating Subtract 17 Miscellaneous Instructions Summary Mnemonic Operation Miscellaneous Instructions Architecture Mask 134Alpha Architecture Handbook Call Privileged Architecture Library Evict Data Cache Block Implementation Note Exception Barrier Prefetch Data 140Alpha Architecture Handbook Implementation Version Memory Barrier Read Processor Cycle Counter Trap Barrier Write Hint Implementation Note Write Memory Barrier Processor Processor j 18 VAX Compatibility Instructions Summary Mnemonic Operation VAX Compatibility Instructions VAX Compatibility Instructions Mnemonic Operation Multimedia Graphics and Video Support Byte and Word Minimum and Maximum Instruction mnemonics Pixel Error Pack Bytes Unpack Bytes Coherency of Memory Access Physical Address Space CharacteristicsIntroduction Software/Hardware Note Granularity of Memory Access Memory-Like and Non-Memory-Like Behavior Width of Memory Access Caches and Write Buffers Translation Buffers and Virtual CachesHardware/Software Coordination Note Page Data Sharing Atomic Update of a Single DatumAtomic Change of a Single Datum STQ Atomic Update of Data Structures 8Alpha Architecture Handbook Ordering Considerations for Shared Data Structures Alpha Shared Memory Model Read/Write Ordering Implementation Note Definition of Processor Issue Constraints Architectural Definition of Processor Issue SequenceDefinition of Before and After 1st↓ 2nd → PiIn=4y,b PiRny,b PiWny,b PiMB PiIMB Processor Issue Constraints Definition of Visibility Definition of Location Access ConstraintsDefinition of Storage Definition of Dependence Constraint Definition of Load-Locked and Store-Conditional PiPj Litmus TestsTimeliness Litmus Test 1 Impossible Sequence Litmus Test 3 Impossible Sequence Litmus Test 2 Impossible Sequence Litmus Test 5 Sequence Okay Litmus Test 4 Sequence OkayLitmus Test 6 Sequence Okay Litmus Test 8 Impossible Sequence Litmus Test 7 Impossible Sequence Litmus Test 10 Sequence Okay Litmus Test 9 Impossible SequenceLitmus Test 11 Impossible Sequence Single Processor Instruction Stream Implied BarriersImplications for Software Single Processor Data Stream See Footnote 1 on First Processor Second Processor Multiprocessor Context SwitchPage Multiprocessor Send/Receive Interrupt Implications for Memory Mapped I/O Multiple Processors Writing to a Single I/O Device Implications for Hardware Dictable Arithmetic Traps PALcode Instructions and Functions PALcode Special Functions Required for PALcode PALcode Environment PALcode Effects on System Code PALcode Replacement PALcode Instructions that Require Recognition Mnemonic Name Required PALcode Instructions IMB Required PALcode Instructions Mnemonic Type OperationDraina Halt Callpal Draina Drain Aborts Callpal Halt Halt Callpal IMB Instruction Memory Barrier Console Subsystem Overview Page Input/Output Overview Page Unprivileged OpenVMS Alpha PALcode OpenVMS Alpha Chmu ChmeChmk Chms Insqhiqr InsqhilInsqhilr Insqhiq Insquel InsqtilrInsqtiq Insqtiqr Remqhil RdpsReadunq REI Remqtiq RemqhiqrRemqtil Remqtilr Swasten RemquelRemqueq Rscc Mfpr Privileged OpenVMS Alpha PalcodeCflush Ldqp Swpctx StqpWtint Page Mnemonic Operation and Description Unprivileged Digital Unix PALcode Privileged Digital Unix PALcode 10-3 10-4Alpha Architecture Handbook Unprivileged Windows NT Alpha PALcode Instruction Summary Unprivileged Windows NT Alpha PALcode Privileged Windows NT Alpha PALcode 11-3 11-4Alpha Architecture Handbook 11-5 Page Hardware-Software Compact Appendix a Instruction Alignment Instruction-Stream ConsiderationsBranch Prediction and Minimizing Branch-Taken Factor Figure A-1 Branch-Format BSR and BR Opcodes Data Alignment Factor Data-Stream ConsiderationsImproving I-Stream Density Factor Instruction Scheduling Factor Shared Data in Multiple Processors Factor Avoiding Cache/TB Conflicts Factor Figure A-3 Bad Allocation in Cache Prefetching Factor Sequential Read/Write Factor Code Sequences Aligned Byte/Word Within Register Memory Accesses Division Stylized Code Forms Byte Swap4.1 NOP Load Literal Clear a Register Booleans Register-to-Register MoveNegate 4.6 not Pseudo-Operations Stylized Code Forms Exceptions and Trap Barriers Software Considerations A-15 Timing Considerations Atomic Sequences Alpha Choices for Ieee Options Appendix B 2Alpha Architecture Handbook Alpha Support for OS Completion Handlers Figure B-1 Ieee Floating-Point Control FPC Quadword Ieee Floating-Point Control FPC QuadwordPage Mapping to Ieee Standard Figure B-2 Ieee Trap Handling Behavior Table B-2 Ieee Floating-Point Trap Handling User Hardware1 Completion Signal Alpha Instructions Code Handler MULx Output Exceptions Cmptlt Cmptle Input Exceptions CVTff Output Exceptions SQRTx Output Exceptions Inexact Division by ZeroOverflow Underflow Common Architecture Instruction Summary Appendix C ADDL/V Table C-2 Common Architecture InstructionsADDQ/V 15.0AF Convert Gfloating to quadword MULQ/V MULL/V SUBQ/V SUBL/V Table C-3 Ieee Floating-Point Instruction Function Codes Ieee Floating-Point Instructions Programming Note VAX Floating-Point Instructions Opcode Summary Independent Floating-Point Instructions Table C-6 Opcode Summary Table C-7 Key to Opcode Summary Symbol Meaning Table C-8 Common Architecture Opcodes in Numerical Order Common Architecture Opcodes in Numerical Order Instruction Summary C-11 Addt Instruction Summary C-13 OpenVMS Alpha PALcode Instruction Summary Mfpripl MfprasnMfpresp Mfprfen Table C-12 Digital Unix Privileged PALcode Instructions Digital Unix PALcode Instruction SummaryMnemonic Opcode Description Table C-14 Windows NT Alpha Privileged PALcode instructions Windows NT Alpha Instruction Summary OpenVMS Alpha PALcode Opcodes in Numerical OrderTable C-15 PALcode Opcodes in Numerical Order Windows NT Wtint 00.003F 00.0063 Table C-17 Opcodes Reserved for PALcode Mnemonic Required PALcode OpcodesOpcodes Reserved to PALcode Table C-16 Required PALcode Opcodes Mnemonic Type OPC01 OPC02 OPC03 OPC04 OPC05 OPC06 OPC07 Opcodes Reserved to CompaqUnused Function Code Behavior Table C-18 Opcodes Reserved for Compaq Mnemonic Table C-19 Ascii Character Set Hex Code Ascii Character Set EV3 Appendix DProcessor Type Assignments Table D-1 Processor Type Assignments Major Type Minor Type PALcode Variation Assignments Digital Unix Architecture Mask and Implementation ValuesTable D-3 Amask Bit Assignments Bit Meaning Table D-4 Implver Value Assignments MeaningPage Waivers Appendix E DECchip 21264 LDxL/STxC with WH64 Violation DECchip 21064/21066/21068 Performance Monitoring Implementation-Specific Functionality For the OpenVMS Alpha Operating System Functions and Arguments for the DECchip 21064/21066/21068 Disable performance monitoring = PCMUX1 Select desired events muxctlSelect performance monitoring options = PCMUX0 Value Description PC1 PC0 Performance Monitor Interrupt Mechanism DECchip 21164/21164PC Performance Monitoring Windows NT Alpha Functions and Argument Input Contents Register Bits Meaning CTR1 CTR0PCSEL0 PCSEL2 OpenVMS Alpha and Digital Unix Functions and ArgumentsModeselect PCSEL1 Select desired events Muxselect Disable performance monitoring do not reset counters Read the counters Select interrupt frequencies Operate on counter MBZ MBZ PCSEL0MBZ PCSEL1 Bits Meaning Counters Operate Under These Modes When Bits SetS U P 6310 Table E-13 21164/21164PC Counter 1 PCSEL1 Event Selection Table E-14 21164/21164PC Counter 2 PCSEL2 Event Selection Value Meaning Table E-15 21164 CBOX1 Event SelectionTable E-16 21164 CBOX2 Event Selection Table E-18 21164PC PM1MUX Event Selection Table E-17 21164PC PM0MUX Event Selection 3 21264 Performance Monitoring PCTR1 SEXTPCTR0CTL47PCTR0 IERCMPCEN0 Bit value Meaning SL1 Select logging options Enable and write selected counters R17/a1 Bits Meaning Table E-26 21264 Enable and Write Counters for OpenVMS Alpha Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13