Table
Bits Meaning When Returned
63:48 Counter 0 returned value
47:32 Counter 1 returned value
31:30 MBZ
29:16 Counter 2 returned value
15:1 MBZ
0 | Set means success; clear means failure |
Table
Bits Meaning
63:48 Counter 0 written value
47:32 Counter 1 written value
31:30 MBZ
29:16 Counter 2 written value
15:0 MBZ
Table E–13: 21164/21164PC Counter 1 (PCSEL1) Event Selection
The following values choose the counter 1 (PCSEL1) event selection:
Value Meaning
0Nothing issued, pipeline frozen
1Some but not all issuable instructions issued
2Nothing issued, pipeline dry
3Replay traps (ldu, wb/maf, litmus test)
4Single issue cycles
5Dual issue cycles
6Triple issue cycles
7Quad issue cycles
8Flow change (all branches,
If PCSEL2 has value 3, flow change is a conditional branch
If PCSEL2 has value 2, flow change is a
Waivers and