Alpha makes it easy to maintain binary compatibility across multiple implementations and easy to maintain full speed on
The Alpha Approach to Byte Manipulation
The Alpha architecture reads and writes bytes between registers and memory with the LDBU and STB instructions. (Alpha also supports word read/writes with the LDWU and STW instructions.)
Byte shifting and masking is performed with normal
The Alpha Approach to Multiprocessor Shared Memory
As viewed from a second processor (including an I/O device), a sequence of reads and writes issued by one processor may be arbitrarily reordered by an implementation. This allows imple- mentations to use multibank caches, bypassed write buffers, write merging, pipelined writes with retry on error, and so forth. If strict ordering between two accesses must be maintained, explicit memory barrier instructions can be inserted in the program.
The basic multiprocessor interlocking primitive is a
Alpha Instructions Include Hints for Achieving Higher Speed
A number of Alpha instructions include hints for implementations, all aimed at achieving higher speed.
•Calculated jump instructions have a target hint that can allow much faster subroutine calls and returns.
•There are prefetching hints for the memory system that can allow much higher cache hit rates.
•There are granularity hints for the
PALcode – Alpha’s Very Flexible Privileged Software Library
A Privileged Architecture Library (PALcode) is a set of subroutines that are specific to a par- ticular Alpha operating system implementation. These subroutines provide
PALcode subroutines are invoked by implementation hardware or by software CALL_PAL instructions.