The performance monitor functions, described in Section E.2.1.2, can provide the following, depending on implementation:
•Enable the performance counters to interrupt and trap into the performance monitoring vector in the operating system.
•Disable the performance counter from interrupting. This does not necessarily mean that the counters will stop counting.
•Select which events will be monitored and set the width of the two counters.
•In the case of OpenVMS Alpha and DIGITAL UNIX, implementations can choose to monitor selected processes. If that option is selected, the PME bit in the PCB controls the enabling of the counters. Since the counters cannot be read/written/reset, if more than one process is being monitored, the rounding error may become significant.
E.2.1.1 DECchip 21064/21066/21068 Performance Monitor Interrupt Mechanism
The performance monitoring interrupt mechanism varies according to the particular operating system.
For the OpenVMS Alpha Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an interrupt to PALcode. The PALcode builds an appropriate stack frame. The PALcode then dis- patches in the form of an exception (not in the form of an interrupt) to the operating system by v e c t o r i n g t o t h e S C B p e r f o r m a n c e m o n i t o r e n t r y p o i n t t h r o u g h S C B B + 6 5 0 (HWSCB$Q_PERF_MONITOR), at IPL 29, in kernel mode.
Two interrupts are generated if both counters overflow. For each interrupt, the status of each counter overflow is indicated by register R4:
R4 = 0 if performance counter 0 caused the interrupt
R4 = 1 if performance counter 1 caused the interrupt
When the interrupt is taken, the PC is saved on the stack frame as the old PC.
For the DIGITAL UNIX Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an interrupt to PALcode. The PALcode builds an appropriate stack frame and dispatches to the operating system by vectoring to the interrupt entry point entINT, at IPL 6, in kernel mode.
Two interrupts are generated if both counters overflow. For each interrupt, registers a0..a2 are as follows:
a0 = osfint$c_perf (4)
a1 = scb$v_perfmon (650)
a2 = 0 if performance counter 0 caused the interrupt a2 = 1 if performance counter 1 caused the interrupt
When the interrupt is taken, the PC is saved on the stack frame as the old PC.
For the Windows NT Alpha Operating System
When a counter overflows and interrupt enabling conditions are correct, the counter causes an interrupt to PALcode. The PALcode builds a frame on the kernel stack and dispatches to the kernel at the interrupt entry point.
