Shift Arithmetic, Sra | Compaq ECQD2KCTE specification

4.5.4 Shift Arithmetic

Format:

SRA	Ra.rq,Rb.rq,Rc.wq	!Operate format
SRA	Ra.rq,#b.ib,Rc.wq	!Operate format

Operation:

Rc ← ARITH_RIGHT_SHIFT(Rav, Rbv<5:0>)

Exceptions:

None

Instruction mnemonics:

SRA	Shift Right Arithmetic

Qualifiers:

None

Description:

Register Ra is right shifted arithmetically 0 to 63 bits by the count in register Rb or a literal. The result is written to register Rc. The sign bit (Rav<63>) is propagated into the vacated bit positions.

4–46Alpha Architecture Handbook

Image 102

Compaq ECQD2KCTE manual Shift Arithmetic, Sra

Contents

Alpha Architecture Handbook October Table of Contents Instruction Formats Page 10.19 Integer Register to Floating-Point Register Move System Architecture and Programming Implications Digital Unix Ieee Floating-Point Conformance Index Figures Tables Xiii Xiv Preface Page Alpha Is a True 64-Bit Architecture ChapterAlpha Approach to Risc Architecture Alpha Is Designed for Very High-Speed Implementations Alpha Instructions Include Hints for Achieving Higher Speed Alpha Approach to Byte ManipulationAlpha Approach to Multiprocessor Shared Memory PALcode Alpha’s Very Flexible Privileged Software Library Data Format Overview Alpha and Programming Languages Instruction Format Overview Instruction OverviewPALcode Instructions Branch Instructions Load/Store InstructionsInteger Operate Instructions Instruction Set Characteristics Terminology and ConventionsFloating-Point Operate Instructions Numbering Security HolesUnpredictable and Undefined Ranges and Extents Aligned and UnalignedUnaligned Should Be Zero SBZ Must Be Zero MBZRead As Zero RAZ Ignore IGNPage Byte AddressingData Types Word Longword Quadword VAX Floating-Point Formats Ffloating Ffloating Load Exponent Mapping Mapf Gfloating Gfloating Register Format Dfloating Ieee Floating-Point Formats SFloating Sfloating Load Exponent Mapping Maps Memory Register Tfloating 13 Tfloating Datum 14 Tfloating Register Format XFloating 15 Xfloating Datum XFloating Big-Endian Formats Longword Integer Format in Floating-Point Unit 17 Xfloating Big-Endian Datum Quadword Integer Format in Floating-Point Unit Data Types with No Hardware Support Big-Endian Addressing Support 23 Little-Endian Byte Addressing 14Alpha Architecture Handbook Integer Registers Alpha RegistersProgram Counter Implementation note Floating-Point Registers Lock Registers Optional Registers NotationProcessor Cycle Counter PCC Register Memory Prefetch Registers Operand Value Notation Meaning Operand NotationOperand Notation Meaning Expression Operand Notation Meaning Instruction Operand Notation Operand Access Type NotationOperand Access Type Notation Meaning Operand Name Notation Operand Data Type Notation Meaning OperatorsOperand Data Type Notation Operators Meaning Bit concatenation Case DIVLoadlocked Priorityencode NotPhysicaladdress LTU Software Note Instruction FormatsNotation Conventions XOR Memory Instruction Format Memory Format Instructions with a Function Code Branch Instruction Format Operate Instruction FormatMemory Format Jump Instructions Floating-Point Operate Instruction Format Floating-Point Operate Instruction Format PALcode Instruction Format Floating-Point Convert InstructionsFloating-Point/Integer Register Moves PALcode Instruction Format Page Instruction Set Overview Instruction Type Section Subsetting Rules Floating-Point Subsets Software Emulation Rules Opcode QualifiersOpcode Qualifiers Meaning Memory Integer Load/Store Instructions Memory Integer Load/Store Instructions Mnemonic Operation Load Address Load Memory Data into Integer Register LDL Implementation Notes Load Unaligned Memory Data into Integer Register Load Memory Data into Integer Register Locked 10Alpha Architecture Handbook Implementation Notes Store Integer Register Data into Memory Conditional Stqc BEQ Hardware/Software Implementation Note Store Integer Register Data into Memory 16Alpha Architecture Handbook Store Unaligned Integer Register Data into Memory Control Instructions Control Instructions Summary Mnemonic Operation JMP BNEBSR JSR Conditional Branch Unconditional Branch Jumps Encoding Meaning Integer Arithmetic Instructions Count instruction CIX extension implementation noteInteger Arithmetic Instructions Summary Mnemonic Operation Longword Add Addl Scaled Longword Add S4ADDLS8ADDL Quadword Add Addq Scaled Quadword Add S4ADDQS8ADDQ Integer Signed Compare Integer Unsigned Compare Count Leading Zero Count Population Count Trailing Zero Longword Multiply Mull Quadword Multiply Mulq Unsigned Quadword Multiply High Longword Subtract Subl Scaled Longword Subtract S4SUBLS8SUBL Quadword Subtract Subq Scaled Quadword Subtract S4SUBQS8SUBQ Logical and Shift Instructions Logical and Shift Instructions Summary Mnemonic Operation Logical Functions Conditional Move Integer Is exactly equivalent to Shift Logical Shift Arithmetic Byte Manipulation Instructions Instruction Meaning Described in Section Insqh InswhInslh Mskbl Compare Byte BEQ Loop To compare two character strings for greater/equal/less Extract Byte Ldqu Optimized examples Big-endian examples Byte Insert 56Alpha Architecture Handbook Byte Mask Insqh Inswh Sign Extend Zero Bytes Subsets and Faults Floating-Point InstructionsSingle-Precision Operations Definitions Alpha finite number Infinity DenormalDirty zero Non-finite number Sign Exponent Fraction Vax EncodingsTrue zero Meaning Finite Rounding Modes VAX Rounding ModesIeee Rounding Modes Computational Models VAX Rounding Mode Instruction NotationIeee Rounding Mode Instruction Notation VAX-Format Arithmetic with Precise Exceptions High-Performance VAX-Format Arithmetic IEEE-Compliant ArithmeticIEEE-Compliant Arithmetic Without Inexact Exception Trapping Modes High-Performance IEEE-Format ArithmeticVAX Trapping Modes When /U or /V mode is specified VAX Trapping Modes Summary Trap Mode Notation Meaning Ieee Trapping Modes Summary of Ieee Trapping Modes Trap Mode Notation Meaning SUI Arithmetic Trap Completion SVI Trap Shadow Length Rules Page Invalid Operation INV Arithmetic Trap Division by Zero DZE Arithmetic Trap Overflow OVF Arithmetic Trap Inexact Result INE Arithmetic Trap Ieee Floating-Point Trap Disable BitsUnderflow UNF Arithmetic Trap Integer Overflow IOV Arithmetic Trap Floating-Point Control Register Fpcr Ieee Denormal Control Bits Ieee Rounding Mode Selected Floating-Point Control Register Fpcr FormatPage Accessing the Fpcr Default Values of the Fpcr Saving and Restoring the FpcrSoftware Notes Floating-Point Instruction Function Field Format Floating-Point Instruction Function Field Contents Meaning for Opcodes 1616 FNC ITOFS/ITOFTSQRTS/SQRTT Unpredictable Ieee Standard Conversion of NaN and Infinity Values Copying NaN Values Generating NaN ValuesPropagating NaN Values Memory Format Floating-Point Instructions Load Ffloating Load Gfloating Load Sfloating Load Tfloating Store Ffloating Store Gfloating Store Sfloating Store Tfloating Branch Format Floating-Point Instructions FBxx Fa.rq,disp.al Branch format Page Floating-Point Operate Format Instructions Adds AddfAddg Ieee Muls MulfMulg Mult Copy Sign Convert Integer to Integer Floating-Point Conditional Move Fcmovne F3,F2,F1 Move from/to Floating-Point Control Register VAX Floating Add Ieee Floating Add Cmpgle VAX Floating CompareCmpgeq Cmpglt Cmptle Ieee Floating CompareCmpteq Cmptlt Convert VAX Floating to Integer Convert Integer to VAX Floating Convert VAX Floating to VAX Floating Convert Ieee Floating to Integer Convert Integer to Ieee Floating Convert Ieee SFloating to Ieee TFloating Convert Ieee TFloating to Ieee SFloating VAX Floating Divide Ieee Floating Divide Floating-Point Register to Integer Register Move Integer Register to Floating-Point Register Move Itofs is exactly equivalent to the sequence VAX Floating Multiply Ieee Floating Multiply VAX Floating Square Root Ieee Floating Square Root VAX Floating Subtract Ieee Floating Subtract Miscellaneous Instructions 17 Miscellaneous Instructions Summary Mnemonic Operation Architecture Mask 134Alpha Architecture Handbook Call Privileged Architecture Library Evict Data Cache Block Implementation Note Exception Barrier Prefetch Data 140Alpha Architecture Handbook Implementation Version Memory Barrier Read Processor Cycle Counter Trap Barrier Write Hint Implementation Note Write Memory Barrier Processor Processor j VAX Compatibility Instructions 18 VAX Compatibility Instructions Summary Mnemonic Operation VAX Compatibility Instructions Multimedia Graphics and Video Support Mnemonic Operation Byte and Word Minimum and Maximum Instruction mnemonics Pixel Error Pack Bytes Unpack Bytes Physical Address Space Characteristics Coherency of Memory AccessIntroduction Granularity of Memory Access Software/Hardware Note Width of Memory Access Memory-Like and Non-Memory-Like Behavior Translation Buffers and Virtual Caches Caches and Write BuffersHardware/Software Coordination Note Page Atomic Update of a Single Datum Data SharingAtomic Change of a Single Datum Atomic Update of Data Structures STQ 8Alpha Architecture Handbook Ordering Considerations for Shared Data Structures Read/Write Ordering Alpha Shared Memory Model Implementation Note Architectural Definition of Processor Issue Sequence Definition of Processor Issue ConstraintsDefinition of Before and After Processor Issue Constraints 1st↓ 2nd → PiIn=4y,b PiRny,b PiWny,b PiMB PiIMB Definition of Location Access Constraints Definition of VisibilityDefinition of Storage Definition of Dependence Constraint Definition of Load-Locked and Store-Conditional Litmus Test 1 Impossible Sequence Litmus TestsTimeliness PiPj Litmus Test 2 Impossible Sequence Litmus Test 3 Impossible Sequence Litmus Test 4 Sequence Okay Litmus Test 5 Sequence OkayLitmus Test 6 Sequence Okay Litmus Test 7 Impossible Sequence Litmus Test 8 Impossible Sequence Litmus Test 9 Impossible Sequence Litmus Test 10 Sequence OkayLitmus Test 11 Impossible Sequence Single Processor Data Stream Implied BarriersImplications for Software Single Processor Instruction Stream See Footnote 1 on Multiprocessor Context Switch First Processor Second ProcessorPage Multiprocessor Send/Receive Interrupt Implications for Memory Mapped I/O Multiple Processors Writing to a Single I/O Device Implications for Hardware Arithmetic Traps Dictable PALcode PALcode Instructions and Functions PALcode Environment Special Functions Required for PALcode PALcode Replacement PALcode Effects on System Code Required PALcode Instructions PALcode Instructions that Require Recognition Mnemonic Name Halt Required PALcode Instructions Mnemonic Type OperationDraina IMB Drain Aborts Callpal Draina Halt Callpal Halt Instruction Memory Barrier Callpal IMB Console Subsystem Overview Page Input/Output Overview Page OpenVMS Alpha Unprivileged OpenVMS Alpha PALcode Chms ChmeChmk Chmu Insqhiq InsqhilInsqhilr Insqhiqr Insqtiqr InsqtilrInsqtiq Insquel REI RdpsReadunq Remqhil Remqtilr RemqhiqrRemqtil Remqtiq Rscc RemquelRemqueq Swasten Ldqp Privileged OpenVMS Alpha PalcodeCflush Mfpr Stqp SwpctxWtint Page Unprivileged Digital Unix PALcode Mnemonic Operation and Description Privileged Digital Unix PALcode 10-3 10-4Alpha Architecture Handbook Unprivileged Windows NT Alpha PALcode Unprivileged Windows NT Alpha PALcode Instruction Summary Privileged Windows NT Alpha PALcode 11-3 11-4Alpha Architecture Handbook 11-5 Page Appendix a Hardware-Software Compact Instruction-Stream Considerations Instruction AlignmentBranch Prediction and Minimizing Branch-Taken Factor Figure A-1 Branch-Format BSR and BR Opcodes Instruction Scheduling Factor Data-Stream ConsiderationsImproving I-Stream Density Factor Data Alignment Factor Shared Data in Multiple Processors Factor Avoiding Cache/TB Conflicts Factor Figure A-3 Bad Allocation in Cache Sequential Read/Write Factor Prefetching Factor Aligned Byte/Word Within Register Memory Accesses Code Sequences Division Byte Swap Stylized Code Forms4.1 NOP Clear a Register Load Literal 4.6 not Register-to-Register MoveNegate Booleans Exceptions and Trap Barriers Pseudo-Operations Stylized Code Forms Software Considerations A-15 Timing Considerations Atomic Sequences Appendix B Alpha Choices for Ieee Options 2Alpha Architecture Handbook Alpha Support for OS Completion Handlers Ieee Floating-Point Control FPC Quadword Figure B-1 Ieee Floating-Point Control FPC QuadwordPage Mapping to Ieee Standard Figure B-2 Ieee Trap Handling Behavior Completion Signal Alpha Instructions Code Handler Table B-2 Ieee Floating-Point Trap Handling User Hardware1 MULx Output Exceptions CVTff Output Exceptions Cmptlt Cmptle Input Exceptions SQRTx Output Exceptions Underflow Division by ZeroOverflow Inexact Appendix C Common Architecture Instruction Summary Table C-2 Common Architecture Instructions ADDL/VADDQ/V 15.0AF Convert Gfloating to quadword MULL/V MULQ/V SUBL/V SUBQ/V Ieee Floating-Point Instructions Table C-3 Ieee Floating-Point Instruction Function Codes VAX Floating-Point Instructions Programming Note Independent Floating-Point Instructions Opcode Summary Table C-7 Key to Opcode Summary Symbol Meaning Table C-6 Opcode Summary Common Architecture Opcodes in Numerical Order Table C-8 Common Architecture Opcodes in Numerical Order Instruction Summary C-11 Addt Instruction Summary C-13 OpenVMS Alpha PALcode Instruction Summary Mfprfen MfprasnMfpresp Mfpripl Digital Unix PALcode Instruction Summary Table C-12 Digital Unix Privileged PALcode InstructionsMnemonic Opcode Description Windows NT Alpha Instruction Summary Table C-14 Windows NT Alpha Privileged PALcode instructions Windows NT PALcode Opcodes in Numerical OrderTable C-15 PALcode Opcodes in Numerical Order OpenVMS Alpha Wtint 00.003F 00.0063 Table C-16 Required PALcode Opcodes Mnemonic Type Required PALcode OpcodesOpcodes Reserved to PALcode Table C-17 Opcodes Reserved for PALcode Mnemonic Table C-18 Opcodes Reserved for Compaq Mnemonic Opcodes Reserved to CompaqUnused Function Code Behavior OPC01 OPC02 OPC03 OPC04 OPC05 OPC06 OPC07 Ascii Character Set Table C-19 Ascii Character Set Hex Code Table D-1 Processor Type Assignments Major Type Minor Type Appendix DProcessor Type Assignments EV3 PALcode Variation Assignments Table D-4 Implver Value Assignments Meaning Architecture Mask and Implementation ValuesTable D-3 Amask Bit Assignments Bit Meaning Digital UnixPage Appendix E Waivers DECchip 21264 LDxL/STxC with WH64 Violation Implementation-Specific Functionality DECchip 21064/21066/21068 Performance Monitoring For the OpenVMS Alpha Operating System Disable performance monitoring Functions and Arguments for the DECchip 21064/21066/21068 = PCMUX0 Select desired events muxctlSelect performance monitoring options = PCMUX1 Value Description PC0 PC1 DECchip 21164/21164PC Performance Monitoring Performance Monitor Interrupt Mechanism Input Contents Register Bits Meaning Windows NT Alpha Functions and Argument CTR0 CTR1PCSEL0 PCSEL1 OpenVMS Alpha and Digital Unix Functions and ArgumentsModeselect PCSEL2 Disable performance monitoring do not reset counters Select desired events Muxselect Select interrupt frequencies Read the counters Operate on counter MBZ PCSEL0 MBZMBZ PCSEL1 Counters Operate Under These Modes When Bits Set Bits MeaningS U P 6310 Table E-13 21164/21164PC Counter 1 PCSEL1 Event Selection Table E-14 21164/21164PC Counter 2 PCSEL2 Event Selection Table E-15 21164 CBOX1 Event Selection Value MeaningTable E-16 21164 CBOX2 Event Selection Table E-17 21164PC PM0MUX Event Selection Table E-18 21164PC PM1MUX Event Selection 3 21264 Performance Monitoring IERCMPCEN0 SEXTPCTR0CTL47PCTR0 PCTR1 SL1 Bit value Meaning Select logging options Enable and write selected counters R17/a1 Bits Meaning Table E-26 21264 Enable and Write Counters for OpenVMS Alpha Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12 Index-13