Compaq ECQD2KCTE manual Ordering Considerations for Shared Data Structures, Software Note

5.5.4 Ordering Considerations for Shared Data Structures

A critical section sequence, such as shown in Section 5.5.3, is conceptually only three steps:

1.Acquire software lock

2.Critical section — read/write shared data

3.Clear software lock

In the absence of explicit instructions to the contrary, the Alpha architecture allows reads and writes to be reordered. While this may allow more implementation speed and overlap, it can also create undesired side effects on shared data structures. Normally, the critical section just described would have two instructions added to it:

<acquire software lock> MB (memory barrier #1)

<critical section – read/write shared data> MB (memory barrier #2)

<clear software lock> <endcode_example>

The first memory barrier prevents any reads (from within the critical section) from being prefetched before the software lock is acquired; such prefetched reads would potentially con- tain stale data.

The second memory barrier prevents any writes and reads in the critical section being delayed past the clearing of the software lock. Such delayed accesses could interact with the next user of the shared data, defeating the purpose of the software lock entirely. It is correct to substitute WMB for the second MB only if:

1.All data locations that are read or written in the critical section are accessed only after acquiring a software lock by using lock_variable (and before releasing the software lock).

2.For each read u of shared data in the critical section, there is a write v such that:

a.v is BEFORE the WMB

b.v follows u in processor issue sequence (see Section 5.6.1.1)

c.v either depends on u (see Section 5.6.1.7) or overlaps u (see Section 5.6.1), or both.

3.Both lock_variable and all the shared data are in memory-like regions (or lock_variable and all the shared data are in non-memory-like regions). If the lock_variable is in a non-memory-like region, the atomic lock protocol must use some implementation-spe- cific hardware support.

Generally, the substitution of a WMB for the second MB increases performance.

Software Note:

In the VAX architecture, many instructions provide noninterruptable read-modify-write sequences to memory variables. Most programmers never regard data sharing as an issue.

In the Alpha architecture, programmers must pay more attention to synchronizing access to shared data; for example, to AST routines. In the VAX architecture, a programmer can use

System Architecture and Programming Implications 5–9