Instruction stream. See I-stream

Instructions, overview, 1–4

INSWH instruction, 4–55

INSWL instruction, 4–55

Integer division, A–10

Integer registers

defined, 3–1

R31 restrictions, 3–1INV bit

See also Arithmetic traps, invalid operation Invalid operation enable (INVE)

FP_C quadword bit, B–6Invalid operation status (INVS)

FP_C quadword bit, B–5

INVD bit. See Trap disable bits, invalid operation

IOV bit

See also Arithmetic traps, integer overflow I-stream

coherency of, 6–8

design considerations, A–2modifying physical, 5–5modifying virtual, 5–5PALcode with, 6–2

with caches, 5–5

ITOFF instruction, 4–124ITOFS instruction, 4–124ITOFT instruction, 4–124

J

JMP instruction, 4–22

JSR instruction, 4–22

JSR_COROUTINE instruction, 4–22

Jump instructions, 4–18 ,4–22

branch prediction logic, 4–22coroutine linkage, 4–23return from subroutine, 4–22unconditional long jump, 4–23 See also Control instructions

L

LDA instruction, 4–5LDAH instruction, 4–5LDBU instruction, 4–6LDF instruction, 4–91LDG instruction, 4–92LDL instruction, 4–6

LDL_L instruction, 4–9

restrictions, 4–10

with processor lock register/flag, 4–10

with STx_C instruction, 4–9LDQ instruction, 4–6

LDQ_L instruction, 4–9

restrictions, 4–10

with processor lock register/flag, 4–10with STx_C instruction, 4–10

LDQ_U instruction, 4–8

LDS instruction, 4–93with FPCR, 4–84LDT instruction, 4–94

LDWU instruction, 4–6

LEFT_SHIFT(x,y) operator, 3–8lg operator, 3–8

Literals, operand notation, 3–5

Litmus tests, shared data veracity, 5–17

Load instructions

emulation of, 4–3

FETCH instruction, 4–139Load address, 4–5

Load address high, 4–5load byte, 4–6

load longword, 4–6load quadword, 4–6

load quadword locked, 4–10

load sign-extended longword locked, 4–9load unaligned quadword, 4–8

load word, 4–6

multiprocessor environment, 5–6serialization, 4–142

See also Floating-point load instructions Load literal, A–12

Load memory integer instructions, 4–4

LOAD_LOCKED operator, 3–8

Load-locked, defined, 5–16

Location, 5–11

Location access constraints, 5–14

Lock flag, per-processor

defined, 3–2

when cleared, 4–10

with load locked instructions, 4–10Lock registers, per-processor

defined, 3–2

with load locked instructions, 4–10Lock variables, with WMB instruction, 4–148

Logical instructions. See Boolean instructions

Longword data type, 2–2

alignment of, 2–12atomic access of, 5–2

LSB (least significant bit), defined for floating-point,

Index–7

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Compaq ECQD2KCTE manual Index-7