Compaq ECQD2KCTE manual Exceptions and Trap Barriers, Pseudo-Operations Stylized Code Forms

A.4.5 Exceptions and Trap Barriers

The EXCB instruction allows software to guarantee that in a pipelined implementation, all pre- vious instructions have completed any behavior that is related to exceptions or rounding modes before any instructions after the EXCB are issued. In particular, all changes to the float- ing-point control register (FPCR) are guaranteed to have been made, whether or not there is an associated exception. Also, all potential floating-point exceptions and integer overflow excep- tions are guaranteed to have been taken.

The TRAPB instruction guarantees that it and any following instructions do not issue until all possible preceding traps have been signaled. This does not mean that all preceding instructions have necessarily run to completion (for example, a Load instruction may have passed all the fault checks but not yet delivered data from a cache miss).

EXCB is thus a superset of TRAPB.

A.4.6 Pseudo-Operations (Stylized Code Forms)

This section summarizes the pseudo-operations for the Alpha architecture that may be used by various software components in an Alpha system. Most of these forms are discussed in preced- ing sections.

In the context of this section, pseudo-operations all represent a single underlying machine instruction. Each pseudo-operation represents a particular instruction with either replicated fields (such as FMOV), or hard-coded zero fields. Since the pattern is distinct, these pseudo-operations can be decoded by instruction decode mechanisms.

In Table A–2,the pseudo-operation codes can be viewed as m acros with parameters. The for- mal form is listed in the left column, and the expansion in the code stream is listed in the right column.

Some instruction mnemonics have synonyms. These differ from pseudo-operations in that each synonym represents the same underlying instruction with no special encoding of operand fields. As a result, synonyms cannot be distinquished from each other. They are not listed in the table. Examples of synonyms are: BIC/ANDNOT, BIS/OR, and EQV/XORNOT.

Table A–2: Decodable Pseudo-Operations (Stylized Code Forms)

Pseudo-Operation			Actual Instruction
in Listing		Meaning	Encoding
BR	target	Branch to target (21-bit signed	BR	R31, target
		displacement)
CLR	Rx	Clear integer register	BIS	R31, R31, Rx
FABS	Fx, Fy	No-exception generic floating	CPYS	F31, Fx, Fy
		absolute value
FCLR	Fx	Clear a floating-point register	CPYS	F31, F31, Fx
FMOV	Fx, Fy	Floating-point move	CPYS	Fx, Fx, Fy

A–14Alpha Architecture Handbook