4.9.1 Conditional Branch
Format:
FBxx | Fa.rq,disp.al | !Branch format |
Operation:
{update PC}
va ← PC + {4*SEXT(disp)}
IF TEST(Fav, Condition_based_on_Opcode) THEN PC ← va
Exceptions: |
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None |
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Instruction mnemonics: |
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FBEQ | Floating Branch Equal |
FBGE | Floating Branch Greater Than or Equal |
FBGT | Floating Branch Greater Than |
FBLE | Floating Branch Less Than or Equal |
FBLT | Floating Branch Less Than |
FBNE | Floating Branch Not Equal |
Qualifiers: |
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None |
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Description:
Register Fa is tested. If the specified relationship is true, the PC is loaded with the target vir- tual address; otherwise, execution continues with the next sequential instruction.
The displacement is treated as a signed longword offset. This means it is shifted left two bits (to address a longword boundary),
The conditional branch instructions are