4.9.1 Conditional Branch

Format:

FBxx

Fa.rq,disp.al

!Branch format

Operation:

{update PC}

va PC + {4*SEXT(disp)}

IF TEST(Fav, Condition_based_on_Opcode) THEN PC va

Exceptions:

 

None

 

Instruction mnemonics:

 

FBEQ

Floating Branch Equal

FBGE

Floating Branch Greater Than or Equal

FBGT

Floating Branch Greater Than

FBLE

Floating Branch Less Than or Equal

FBLT

Floating Branch Less Than

FBNE

Floating Branch Not Equal

Qualifiers:

 

None

 

Description:

Register Fa is tested. If the specified relationship is true, the PC is loaded with the target vir- tual address; otherwise, execution continues with the next sequential instruction.

The displacement is treated as a signed longword offset. This means it is shifted left two bits (to address a longword boundary), sign-extended to 64 bits, and added to the updated PC to form the target virtual address.

The conditional branch instructions are PC-relative only. The 21-bit signed displacement gives a forward/backward branch distance of +/–1M instructions.

4–100Alpha Architecture Handbook

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Image 156
Compaq ECQD2KCTE manual FBxx Fa.rq,disp.al Branch format