Texas Instruments TMS320TCI648x manuals
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Texas Instruments TMS320TCI648x Manual
256 pages 2.51 Mb
3 Contents14 Read This FirstAbout This Manual Notational Conventions Related Documentation From Texas Instruments 1 Overview 1.1 General RapidIO System User's Guide 16 Serial RapidIO (SRIO)Overview 17 Figure 1. RapidIO Architectural Hierarchy18 1.1.2 RapidIO Interconnect Architecture1.1.3 Physical Layer 1x/4x LP-Serial Specification18 Serial RapidIO (SRIO) SPRUE13A September 2006Submit Documentation Feedback Overview (1) InfiniBand is a trademark of the InfiniBand Trade Association. 19 1.2 RapidIO Feature Support in SRIO21 2 SRIO Functional Description 2.1 OverviewPacketGeneration Bufferingaddressanddatahandoff 22 2.1.2 SRIO Packets2.1.2.1 Operation Sequence Figure 4. SRIO Peripheral Block Diagram 23 2.1.2.2 Example Packet Streaming WritePHY=Physicallayer TRA= Transportlayer LOG=Logicallayer 24 2.1.2.3 Control SymbolsSCorPD parameter1stype0 stype1Parameter0 cmd CRC 533553 Delimiter 1stByte 2ndByte 3rdByte 8 Figure 6. 1x/4x RapidIO Packet Data Stream (Streaming-Write Class)Note: Figure 6 assumes that addresses are 32-bit and device IDs are 8-bit. Figure 7. Serial RapidIO Control Symbol Format 2.1.2.4 SRIO Packet Type 25 2.2 SRIO Pins26 2.3 Functional Operation83 3 Logical/Transport Error Handling and Logging85 4 Interrupt Conditions 4.1 CPU Interrupts4.2 General Description 86 4.3 Interrupt Condition Status and Clear Registers93 4.4 Interrupt Condition Routing Registers97 4.5 Interrupt Status Decode Registers100 4.8 Interrupt Handling102 5 SRIO Registers 5.1 Introduction111 5.2 Peripheral Identification Register (PID)112 5.3 Peripheral Control Register (PCR)Table 42. Peripheral Control Register (PCR) Field Descriptions 113 5.4 Peripheral Settings Control Register (PER_SET_CNTL)116 5.5 Peripheral Global Enable Register (GBL_EN)117 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)119 5.7 Block n Enable Register (BLK n_EN)Figure 68. Block nEnable Register (BLK n_EN) Table 47. Block nEnable Register (BLK n_EN) Field Descriptions 120 5.8 Block n Enable Status Register (BLK n_EN_STAT)Figure 69. Block nEnable Status Register (BLK n_EN) Table 49. Block nEnable Status Register (BLK n_EN_STAT) Field Descriptions 121 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)122 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)123 5.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTL n)124 5.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTL n)Figure 73. Packet Forwarding Register nfor 8-Bit Device IDs (PF_8B_CNTL n) Table 55. Packet Forwarding Register nfor 8-Bit DeviceIDs (PF_8B_CNTL n) Field Descriptions 125 5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRX n_CNTL)128 5.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTX n_CNTL)Figure 75. SERDES Transmit Channel Configuration Register n(SERDES_CFGTX n_CNTL) Table 60. SERDES Transmit Channel Configuration Register n(SERDES_CFGTX n_CNTL) FieldDescriptions 129 Table 61. DE Bits of SERDES_CFGTX n_CNTLTable 62. SWING Bits of SERDES_CFGTX n_CNTL 130 5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL)132 5.16 DOORBELL n Interrupt Condition Status Register (DOORBELL n_ICSR)Figure 77. Doorbell nInterrupt Condition Status Register (DOORBELL n_ICSR)31 16 Table 66. DOORBELL nInterrupt Condition Status Register (DOORBELL n_ICSR) Field Descriptions 133 5.17 DOORBELL n Interrupt Condition Clear Register (DOORBELL n_ICCR)Figure 78. Doorbell nInterrupt Condition Clear Register (DOORBELL n_ICCR)31 16 Table 68. DOORBELL nInterrupt Condition Clear Register (DOORBELL n_ICCR) Field Descriptions 134 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)135 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)136 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)137 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)138 5.22 LSU Interrupt Condition Status Register (LSU_ICSR)141 5.23 LSU Interrupt Condition Clear Register (LSU_ICCR)142 5.24 Error, Reset, and Special Event Interrupt Condition Status Register(ERR_RST_EVNT_ICSR) 143 5.25 Error, Reset, and Special Event Interrupt Condition Clear Register(ERR_RST_EVNT_ICCR) 144 5.26 DOORBELL n Interrupt Condition Routing Registers (DOORBELL n_ICRR andDOORBELL n_ICRR2)Table 78. DOORBELL nInterrupt Condition Routing Register Field Descriptions 145 5.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2)Table 79. RX CPPI Interrupt Condition Routing Register Field Descriptions 146 5.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)Table 80. TX CPPI Interrupt Condition Routing Register Field Descriptions 147 5.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0LSU_ICRR3)149 5.30 Error, Reset, and Special Event Interrupt Condition Routing Registers(ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3)Table 82. Error, Reset, and Special Event Interrupt Condition Routing Register Field Descriptions 150 5.31 Interrupt Status Decode Register (INTDST n_DECODE)Table 84. Interrupt Status Decode Register (INTDST n_DECODE) Field Descriptions 154 5.32 INTDST n Interrupt Rate Control Register (INTDST n_RATE_CNTL)155 5.33 LSU n Control Register 0 (LSU n_REG0)156 5.34 LSU n Control Register 1 (LSU n_REG1)157 5.35 LSU n Control Register 2 (LSU n_REG2)158 5.36 LSU n Control Register 3 (LSU n_REG3)159 5.37 LSU n Control Register 4 (LSU n_REG4)Figure 98. LSU nControl Register 4 (LSU n_REG4) Table 96. LSU nControl Register 4 (LSU n_REG4) Field Descriptions 160 5.38 LSU n Control Register 5 (LSU n_REG5)161 5.39 LSU n Control Register 6 (LSU n_REG6)Figure 100. LSU nControl Register 6 (LSU n_REG6) Table 100. LSU nControl Register 6 (LSU n_REG6) Field Descriptions 162 5.40 LSU n Congestion Control Flow Mask Register (LSU n_FLOW_MASKS)Figure 101. LSU nCongestion Control Flow Mask Register (LSU n_FLOW_MASKS) Table 102. LSU nCongestion Control Flow Mask Register (LSU n_FLOW_MASKS) Field Descriptions Figure 102. LSU nFLOW_MASK Fields Table 103. LSU nFLOW_MASK Fields 163 Table 103. LSU nFLOW_MASK Fields (continued)164 5.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP)Figure 103. Queue nTransmit DMA Head Descriptor Pointer Register (QUEUE n_TXDMA_HDP) 165 5.42 Queue n Transmit DMA Completion Pointer Register (QUEUE n_TXDMA_CP)Figure 104. Queue nTransmit DMA Completion Pointer Register (QUEUE n_TXDMA_CP) Table 107. Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP) FieldDescriptions 166 5.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP)Figure 105. Queue nReceive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP) Table 109. Queue nReceive DMA Head Descriptor Pointer Register (QUEUE n_RXDMA_HDP) FieldDescriptions 167 5.44 Queue n Receive DMA Completion Pointer Register (QUEUE n_RXDMA_CP)Figure 106. Queue nReceive DMA Completion Pointer Register (QUEUE n_RXDMA_CP) Table 111. Queue nReceive DMA Completion Pointer Register (QUEUE n_RXDMA_CP) FieldDescriptions 168 5.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)Table 112. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions 169 5.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[07])172 5.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)Table 115. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions 173 5.48 Receive CPPI Control Register (RX_CPPI_CNTL)Table 116. Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions 174 5.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[03])177 5.50 Mailbox to Queue Mapping Registers (RXU_MAP_L n and RXU_MAP_H n)181 5.51 Flow Control Table Entry Register n (FLOW_CNTL n)Figure 114. Flow Control Table Entry Register n(FLOW_CNTL n) Table 122. Flow Control Table Entry Register n(FLOW_CNTL n) Field Descriptions 182 5.52 Device Identity CAR (DEV_ID)183 5.53 Device Information CAR (DEV_INFO)184 5.54 Assembly Identity CAR (ASBLY_ID)185 5.55 Assembly Information CAR (ASBLY_INFO)186 5.56 Processing Element Features CAR (PE_FEAT)188 5.57 Source Operations CAR (SRC_OP)Table 128. Source Operations CAR (SRC_OP) Field Descriptions 189 5.58 Destination Operations CAR (DEST_OP)Table 129. Destination Operations CAR (DEST_OP) Field Descriptions 190 5.59 Processing Element Logical Layer Control CSR (PE_LL_CTL)Table 130. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions 191 5.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)192 5.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)193 5.62 Base Device ID CSR (BASE_ID)194 5.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)195 5.64 Component Tag CSR (COMP_TAG)196 5.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)197 5.66 Port Link Time-Out Control CSR (SP_LT_CTL)Table 137. Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions 198 5.67 Port Response Time-Out Control CSR (SP_RT_CTL)Table 138. Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions 199 5.68 Port General Control CSR (SP_GEN_CTL)Table 139. Port General Control CSR (SP_GEN_CTL) Field Descriptions 200 5.69 Port Link Maintenance Request CSR n (SP n_LM_REQ)201 5.70 Port Link Maintenance Response CSR n (SP n_LM_RESP)Figure 133. Port Link Maintenance Response CSR n(SP n_LM_RESP) Table 143. Port Link Maintenance Response CSR n(SP n_LM_RESP) Field Descriptions 202 5.71 Port Local AckID Status CSR n (SP n_ACKID_STAT)Figure 134. Port Local AckID Status CSR n(SP n_ACKID_STAT) Table 145. Port Local AckID Status CSR n(SP n_ACKID_STAT) Field Descriptions 203 5.72 Port Error and Status CSR n (SP n_ERR_STAT)206 5.73 Port Control CSR n (SP n_CTL)209 5.74 Error Reporting Block Header Register (ERR_RPT_BH)210 5.75 Logical/Transport Layer Error Detect CSR (ERR_DET)212 5.76 Logical/Transport Layer Error Enable CSR (ERR_EN)214 5.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)215 5.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)216 5.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)217 5.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)218 5.81 Port-Write Target Device ID CSR (PW_TGT_ID)219 5.82 Port Error Detect CSR n (SP n_ERR_DET)221 5.83 Port Error Rate Enable CSR n (SP n_RATE_EN)223 5.84 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0)Figure 147. Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) Table 163. Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) FieldDescriptions 224 5.85 Port n Error Capture CSR 1 (SP n_ERR_CAPT_DBG1)225 5.86 Port n Error Capture CSR 2 (SP n_ERR_CAPT_DBG2)226 5.87 Port n Error Capture CSR 3 (SP n_ERR_CAPT_DBG3)227 5.88 Port n Error Capture CSR 4 (SP n_ERR_CAPT_DBG4)228 5.89 Port Error Rate CSR n (SP n_ERR_RATE)Figure 152. Port Error Rate CSR n(SP n_ERR_RATE) Table 173. Port Error Rate CSR n(SP n_ERR_RATE) Field Descriptions 229 5.90 Port Error Rate Threshold CSR n (SP n_ERR_THRESH)Figure 153. Port Error Rate Threshold CSR n(SP n_ERR_THRESH) Table 175. Port Error Rate Threshold CSR n(SP n_ERR_THRESH) Field Descriptions 230 5.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER)Table 176. Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER) FieldDescriptions 231 5.92 Port IP Mode CSR (SP_IP_MODE)233 5.93 Port IP Prescaler Register (IP_PRESCAL)Table 178. Port IP Prescaler Register (IP_PRESCAL) Field Descriptions 234 5.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[03])Table 179. Port-Write-In Capture CSR Field Descriptions 235 5.95 Port Reset Option CSR n (SP n_RST_OPT)236 5.96 Port Control Independent Register n (SP n_CTL_INDEP)238 5.97 Port Silence Timer n Register (SP n_SILENCE_TIMER)Figure 160. Port Silence Timer nRegister (SP n_SILENCE_TIMER) Table 185. Port Silence Timer nRegister (SP n_SILENCE_TIMER) Field Descriptions 239 5.98 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS)240 5.99 Port Control Symbol Transmit n Register (SP n_CS_TX)Figure 162. Port Control Symbol Transmit nRegister (SP n_CS_TX) Table 189. Port Control Symbol Transmit nRegister (SP n_CS_TX) Field Descriptions Index 241 Index
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