Intel 41210 manual Introduction1, PCI Express* Interface Features, PCI-X Interface Features

Introduction

Introduction1

The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210) integrates two PCI Express*-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express* port is compatible with the PCI Express* Specification, Revision 1.0a. The two PCI bus interfaces are comparable with the PCI Local Bus Specification, Revision 2.3 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.

1.1PCI Express* Interface Features

•PCI Express* Specification, Revision 1.0a

•Support for single ×8, single ×4 or single x1 PCI Express* operation

•64-bit addressing support

•32-bit CRC (cyclic redundancy checking) covering all transmitted data packets

•16-bit CRC on all link message information

•Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s

•Maximum realized bandwidth on PCI Express* interface of 2 GB/s (in ×8 mode) in each direction simultaneously, for an aggregate of 4 GB/s

1.2PCI-X Interface Features

•PCI Local Bus Specification, Revision 2.3

•PCI-to-PCI Bridge Specification, Revision 1.1

•PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b

•64-bit 66 MHz, 3.3 V, not 5 V tolerant

• On-Die Termination (ODT) with 8.3 KΩ pull-up to 3.3 V for PCI signals

•Six external REQ/GNT pairs for internal arbiter on segment A and B respectively

•Programmable bus parking on either the last agent or always on Intel® 41210 Serial to Parallel PCI Bridge

•Two-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)

•External PCI clock-feed support for asynchronous primary and secondary domain operation

•64-bit addressing for upstream and downstream transactions

•Downstream LOCK# support

•No upstream LOCK# support

•PCI fast Back-to-Back capable as target

•Up to four active and four pending upstream memory read transactions

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 11