Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 71
Error Handling
11.2.2.2 Split Termination on PCI-X Interface
A split-termination error translation occurs when a completion-required transaction receives a
“split termination” response when originally mastered on the PCI-X bus, and a “split completion”
error message is later received for the original request. Table 30 describes the completion-status
translation for PCI-X split-completion terminations. The behavior described in Tabl e 30 is
independent of the Master Abort Mode bit and whether or not the cycle is exclusive (locked).
Note: When a target or master abort is returned on PCI Express* for the first read of an exclusive access,
the secondary PCI-X bus is not locked. This is especially important in regard to the completion
messages “byte count out of range, “device specific”, and “reserved/invalid codes”. The 41210
Bridge does not lock its bus on these errors, even though they are not explicitly master- or target-
aborts on the PCI-X interface.
Table 30. Completion-Status Translation for PCI-X Split-Completion Terminations
PCI-X Split Termination Message PCI Express*
Completion Status
Class Index
Successful 0 00h Successful
Master abort 1 00h UR
Target abort 1 01h CA
Write data parity error 1 02h UR
Byte count out of range 2 00h UR
Write data parity error 2 01h UR
Device-specific 2 8Xh CA
Reserved/invalid Others CA