20 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Signal Description
2.7 Reset Straps

The following signals are used for static configuration. These signals are all sampled on the rising

edge of PERST#.

Table 7. Reset Strap Pins

Signal I/O Description
A_133EN
B_133EN I
PCI-X 133 MHz Enable: The 133EN pin, when high, allows the PCI-X segment to run at 133 MHz
when X_PCIXCAP is sampled high. When 133EN is low, the PCI-X segment runs only at 100MHz
when X_PCIXCAP is sampled high.
To tie high: Use an approximately 8.2KΩ resistor to pull to VCC33.
To tie low: Pull down to ground.
A_STRAP[6:0]
B_STRAP[6:0] I
Internal Test Modes: For normal operation, X_STRAP[6] and [2:0] must be pulled low and
X_STRAP[5:3] must be pulled high, as shown in the table below.
To tie high: Use approximately an 8.2KΩ resistor to pull up to VCC33.
To tie low: Pull down to VSS.
A_TEST[2:1]
B_TEST{2:1] IInternal Test Modes: These straps must be pulled high to VCC33. Use an approximately 8.2 KΩ
resistor to pull up to VCC33.
CFGRETRY I
Configuration Retry: This pin, when sampled high, sets the Configuration Cycle Retry Bit (bit 3) in
the Bridge Initialization Register (“Offset FCh: BINIT—Bridge Initialization Register” on page 104).
When no local initialization is needed, this pin must be pulled low to VSS.
See Section 9, “Local Initialization” for additional details.
Tot al 19
X_STRAP Logic Level
00
10
20
31
41
51
60