Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 7
Contents
Tables1 ODT Signals ........................................................................................................ .......................14
2 PCI Express* Inte rface Pins ................................................................................ .......................15
3 PCI Interface Pins ............................................................................ ...........................................16
4 PCI Interface Pi ns: 64-Bit Extensions................................. ........................................................18
5 PCI Clock and Res et Pins ............................................................................ ..............................18
6 Interrupt Interfac e Pins ........................................................................................ .......................19
7 Reset Strap Pin s........................................................................ .................................................20
8 SMBus Interface P ins............ ..................................................................................................... 21
9 Miscellaneous Pins.................................... ................................................................................. 22
10 Miscellaneous Pins.................................... ................................................................................. 23
11 PCI Mode Pin/S trap Encoding......................... ........................................................................... 25
12 PCI-X Initiali zation Pattern......................................................... .................................................25
13 PCI Transactions Sup ported....................................................................................................... 26
14 PCI-X Transactio ns Supported........................ ........................................................................... 27
15 LOCK Tran saction Handling in the Intel® 41210 Serial to Parallel PCI Bridge ...........................29
16 Intel® 41210 Serial to Parallel PCI Bridge Implementation of Requester Attribute Fie lds.......... 34
17 Intel® 41210 Serial to Parallel PCI Bridge Implementation of Completer Attribute Fields .......... 35
18 Split Comple tion Abort Registers............................................... .................................................35
19 Addressable Spaces within the Intel® 41210 Serial to Parallel PCI Bridge................................ 41
20 Secondary PCI Dev ice Addressing......................................................................................... ....42
21 Upstream Transaction Orderin g .................................................................................................51
22 Downstream Transacti on Ordering............................................................... ..............................52
23 INTx Routing Tabl e.......................................................................... ...........................................53
24 Interrupt Binding for Devices behind a Bridge ............................................................................ 54
25 SMBus Address As signments ............................................................................. .......................55
26 SMBus Command E ncoding............................................................................................. ..........56
27 SMBus Status B yte Encoding.......................................................... ...........................................57
28 Clock Domains ........................................................................................................... .................65
29 Completion-Stat us Translation for Immediate Terminations............................................. ..........70
30 Completion-S tatus Translation for PCI-X Split-Completion Terminations ........... .......................71
31 Completion-S tatus Translation for PCI Express* Split-Completion Terminations............. ..........72
32 Bit Attribute De finitions ................................................................................. ..............................73
33 Legacy Configurati on Space...................................................................................... .................76
34 PCI Express* Extended Configuration Space .............................................. ..............................77
35 Offset 00h: ID— Identifiers ................................................................................... .......................78
36 Offset 04h: PC ICMD—Command Register ......................................................... .......................78
37 Offset 06h: PSTS —Primary Device Status............................................................................. ....79
38 Offset 08h: REVID —Revision ID ................................................................................................ 80
39 Offset 09h: CC— Class Code..................................................... .................................................81
40 Offset 0Ch: CLS— Cache Line Size................................................. ...........................................81
41 Offset 0Dh: PM LT—Primary Master Latency Timer ................................................................... 81
42 Offset 0Eh: HEA DTYP—Header Type ............................................................................. ..........81
43 Offset 18h: BNUM— Bus Numbers ............................................................................................. 82
44 Offset 1Bh: SML T—Secondary Master Latency Timer........................................ .......................82
45 Offset 1Ch: IOBL —I/O Base and Limit ....................................................................................... 83
46 Offset 1Eh: SSTS —Secondary Status ...................................................................... .................84
47 Offset 20h: MBL—Mem ory Base and Lim it ................................................................................ 85
48 Offset 24h: P MBL—Prefetchable Memory Base and Limit.............. ...........................................86
49 Offset 28h: PMB U32—Prefetchable Memory Base Upper 32 Bits ............................................. 86