Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 85
Register Description
12.2.13 Offset 20h: MBL—Memory Base and Limit
Defines the base and limit, aligned to a 1 MB boundary, of the non-prefetchable memory area of
the bridge. Accesses from PCI Express* that are within the ranges specified in this register are sent
to PCI when the Memory Space Enable bit is set. Accesses from PCI that are outside the ranges
specified are forwarded to PCI Express* when the Bus Master Enable bit is set.
Note: Even though this region is non-prefetchable, peer reads from PCI can potentially prefetch through
this window. This prefetching can be turned off with the Prefetch Policy bits (PP bits[42:41],
“Offset 178h: PREFCTRL—Prefetch Control Register” on page119).
These registers are cleared to all 0s on reset.
Note: This register must be programmed appropriately to enable or disable the space.
Table 47. Offset 20h: MBL—Memory Base and Limit
Bits Type Reset Description
31:20 RW 000h Memory Limit (ML): These bits are compared with bits[31:20] of the incoming address to
determine the upper 1 MB-aligned value (exclusive) of the range. The incoming address
must be less than this value.
19:16 RO 0h Reserved
15:4 RW 000h Memory Base (MB): These bits are compared with bits[31:20] of the incoming address to
determine the lower 1 MB-aligned value (inclusive) of the range. The incoming address
must be greater than or equal to this value.
3:0 RO 0h Reserved