Offset 08h REVID-Revision ID, Bits | Intel 41210 manual

Register Description
Table 37.		Offset 06h: PSTS—Primary Device Status (Sheet 2 of 2)

Bits		Type	Reset	Description

				Signaled Target Abort (STA): This bit is set when a completion packet with Completer
11		RWC	0b	Abort (CA) status is generated on PCI Express*.
11		RWC	0b	0 = No error.
				0 = No error.
				1 = Completer Abort (CA) status transmitted on PCI Express* interface

10:9		RO	00b	DEVSEL# Timing (DVT): These bits have no meaning on PCI Express*. Fast decode
10:9		RO	00b	timing is reported.
				timing is reported.

				Master Data Parity Error Detected (MDPD): This bit is set when the 41210 detects an
				uncorrectable data error. This bit is set when the parity error response enable bit (PERE) in
				the Command Register (“Offset 04h: PCICMD—Command Register” on page 78) is set and
				one of the following conditions occurs:
8		RWC	0b	• The bridge receives a completion with a poisoned TLP on the PCI Express* interface.
8		RWC	0b	• The bridge receives a completion with poisoned data on the peer PCI segment.

				• The bridge poisons a write request on the PCI Express* interface.
				0 = No error
				1 = Data Parity Error in completion packet received or a write request transmitted

7		RO	0b	Fast Back-to-Back Capable (FBC): This bit has no meaning on PCI Express*.

6		RO	0b	Reserved

5		RO	0b	66 MHz Capable (C66): This bit has no meaning on PCI Express*.

				Capabilities List Enable (CAPE): This bit indicates the capabilities pointer in the 41210.
4		RO	1b	Offset 34H indicates the offset for the first entry in the linked list of capabilities.
4		RO	1b	0 = No capabilities enabled
				0 = No capabilities enabled
				1 = Capabilities enabled and accessible from 34H

3		RO	0b	Interrupt Status: The 41210 does not generate internal interrupts. This bit is hard-wired
3		RO	0b	to 0.
				to 0.

2:0		RO	0h	Reserved

12.2.4Offset 08h: REVID—Revision ID

This register is the Revision ID Register.

Table 38.		Offset 08h: REVID—Revision ID

Bits		Type	Reset	Description

				Revision ID (RID): These bits indicate the stepping (die version) of the Intel® 41210 Serial
7:0		RO	00h	to Parallel PCI Bridge.
				0000 0000 A-0 stepping

80	Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Image 80

Intel 41210 manual Offset 08h REVID-Revision ID, Offset 06h PSTS-Primary Device Status Sheet 2, Bits

Contents

Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision Description Introduction1 PCI Express* Interface FeaturesPCI-X Interface Features Jtag Power ManagementSMBus Interface Signal Description On-Die Termination ODT ODT Signals AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74ADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50 PCI Express* Interface Pins PCI Express* InterfacePERCOMP10 Total PCI Interface Pins Sheet 1 PCI Bus Interface Two InstancesADEVSEL# AIRDY# PCI Interface Pins Sheet 2 PCI Bus Interface 64-Bit Extension Two Interfaces PCI Interface Pins 64-Bit ExtensionsPCI Clock and Reset Pins Interrupt Interface Pins Interrupt Interface Two InterfacesAINTA# AINTB# AINTC# AINTD# Cfgretry Reset StrapsReset Strap Pins SMBus Interface Pins Miscellaneous Pins Miscellaneous Pins Voltage Pins Number Description This page Intentionally Left Blank PCI Mode Pin/Strap Encoding PCI-X InterfaceInitialization PCI-X Initialization Pattern PCI Mode Transactions SupportedPCI Transactions Supported Transaction Encoding1 PCI-X Transactions Supported PCI-X ModeRead Transactions Configuration Transactions Delayed PCI Lock CyclesEnd Point Source Decoding Transaction Termination PCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface PCI-X Protocol Specifics Attributes2 4 GB and 4 K Page Crossover Wait States Arbitration Split TransactionsFields Split Completion Abort Registers Internal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01 Power Management Hardware-Controlled Active State Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power Management Power-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressable Space Access PCI-to-PCI Bridge a Configuration SpacePCI-to-PCI Bridge B Configuration Space Addressing5 Configuration-Space Access PCI Express* Configuration AccessDevice Number Signal Used for Public/Private Secondary PCI Devices Addressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-X I/O Space Access Mechanism SMBus Configuration Access O Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory Forwarding Opaque Memory Window VGA AddressingPrefetchable Memory Window § § Transaction Ordering Upstream Transaction OrderingUpstream Transaction Ordering Row Pass Column Downstream Transaction Ordering Downstream Transaction OrderingRelaxed Ordering/No-Snoop Support INTx Routing Table Interrupt SupportLegacy Interrupt Sharing Interrupt Routing for Devices behind a Bridge Interrupt Binding for Devices behind a BridgeDevice Number on Secondary Bus Bit Value System Management Bus InterfaceSMBus Address Assignments SMBus Commands SMBus Command EncodingInternal Command SMBus command SMBus Status Byte Encoding ConfigurationInitialization Sequence Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock and Reset Device ResetClocking Clock Domains PCI Express* Reset Mechanism PERST# Reset MechanismRSTIN# Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Errors Error HandlingPCI Express* Errors Error Types Termination of Completion Required TransactionsCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* Completion Successful 00h PCI-X Split Termination Message PCI ExpressIndex Split Termination on PCI Express* Interface PCI Express* Completion Status PCI Completion Register Nomenclature and Access Attributes PERST# resetRegister Description Bit Attribute Definitions Configuration Registers PCI/PCI-X Compatible Configuration region Capptr0xFFF 0x300 0x100 0x40 0x00 B3174-02 Legacy Configuration Space Byte Offset PCI Express* Extended Configuration SpaceRegister Offset 04h PCICMD-Command Register Offset 04h PCICMD-Command Register Sheet 1Reset Description Offset 00h ID-Identifiers Offset 04h PCICMD-Command Register Sheet 2 Offset 06h PSTS-Primary Device StatusOffset 06h PSTS-Primary Device Status Sheet 1 Type Offset 08h REVID-Revision ID Offset 06h PSTS-Primary Device Status Sheet 2Offset 08h REVID-Revision ID Bits Offset 0Dh PMLT-Primary Master Latency Timer Offset 09h CC-Class CodeOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header Type Offset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus Numbers Offset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing only Offset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status Offset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this value Bits Type Reset Description Offset 24h PMBL-Prefetchable Memory Base and LimitOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and Limit Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 Bits Offset 30h IOBLU16-I/O Base and Limit Upper 16 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt Information Offset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed Transactions Offset 42h MTT-Multi-Transaction Timer Offset 43h PCLKC-PCI Clock ControlOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item Pointer Offset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxPayloadSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxReadRequestSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 50h EXPLCAP-PCI Express* Link Capabilities Register Bits Type Default Description Offset 54h EXPLCTL-PCI Express* Link Control RegisterOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit Latency Offset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 6Ch PMCAPID-Power Management Capabilities Identifier Offset 5Eh MSIMC-PCI Express* MSI Message ControlOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management CapabilitiesOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management Capabilities Offset 73h PMDATA-Power Management Data Field Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 72h PMBSE-Power Management Bridge Support Extensions Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item PointerOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item Pointer Offset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary Status Offset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction ControlOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization Register Power Budgeting Capability as the next capability Advanced Error Reporting Extended Capability Version NumberID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abort Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Unsupported Request Error Status Severity Flow Control Protocol Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supported Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask 1270 Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header LogOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Sheet 1 Sheet 2 Logs the header Internal Bridge Data Error Mask PCI Delayed Transaction Timer Expiry MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected Mask PCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort Mask Internal Bridge Data Error Severity PCI Delayed Transaction Timer Expiry SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected Severity Register is cleared by the software writing a 1 to the bit Rwcs = Errnonfatal = ErrfatalPCI-X Detected Split Completion Master Abort Severity Type Reset Description Offset 16Ah ARBCNTRL-Internal Arbiter Control RegisterOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS1 6360 RsvdP Offset 178h PREFCTRL-Prefetch Control RegisterOffset 178h PREFCTRL-Prefetch Control Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register