Intel 41210 2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces), 2.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces)

18 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Signal Description

2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces)2.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces)

Table 4. PCI Interface Pins: 64-Bit Extensions

Signal I/O Description

A_AD[63:32]

B_AD[63:32] I/O

PCI Address/Data: The AD signals are a multiplexed address and data bus. This bus provides an

additional 32 bits to the PCI bus. During the data phases of a transaction, the initiator drives the

upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when

REQ64# and ACK64# are both asserted.

A_C/BE#[7:4]

B_C/BE#[7:4] I/O

Bus Command and Byte enables upper 4bits: The C/BE# signals are a multiplexed command

field and byte enable field. For both reads and write transactions, the initiator drives byte enables for

the AD[63:32] data bits on C/BE[7:4] during the data phases when REQ64# and ACK64# are both

asserted.

A_PAR64

B_PAR64 I/O PCI interface upper 32bits parity: PAR64 carries the even parity of the 36 bits of AD[63:32] and

C/BE#[7:4] for both address and data phases.

A_REQ64#

B_REQ64# I/O PCI interface request 64-bit transfer: REQ64# is asserted by the initiator to indicate that the

initiator is requesting a 64-bit data transfer. REQ64# has the same timing as FRAME#. When the

41210 is the initiator, this signal is an output. When the 41210 is the target, this signal is an input.

A_ACK64#

B_ACK64# I/O PCI interface acknowledge 64-bit transfer: ACK64# is asserted by the target only when REQ64# is

asserted by the initiator, to indicate the target ability to transfer data using 64 bits. ACK64# has the

same timing as DEVSEL#.

Tota l 78

Table 5. PCI Clock and Reset Pins

Signal I/O Description

A_CLKO[6:0]

B_CLKO[6:0] O

PCI Clock Output: CLKO is the 33/66/100/133 MHz clock for a PCI device. X_CLK[6] must be

connected to the respective X_CLKIN input for feeding the PCI interface logic. Unused clock outputs

may be disabled via the “Offset 43h: PCLKC—PCI Clock Control” register and should be treated as

no connects on the board.

A_CLKIN

B_CLKIN IPCI Clock In: CLKIN is the PCI clock feedback input. CLKIN must be connected to the

corresponding X_CLKO[6] through a 22 Ω ± 1% series resistor.

A_RST#

B_RST# OPCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus.

A_PME#

B_PME# I

PCI Power Management Event: PME# is the PCI bus power management event signal. PME# is a

shared open-drain input from all the PCI cards on the corresponding PCI bus segment. PME# is a

level-sensitive signal that is converted to a PME event on PCI Express*.

PME# does not have on-die 8.3 KΩ pull-up. This pull-up must be provided externally.

Tota l 20