Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 81
Register Description
12.2.5 Offset 09h: CC—Class Code
This register contains the class code, sub-class code, and programming interface for the device.
12.2.6 Offset 0Ch: CLS—Cache-Line Size
This register indicates the cache-line size of the system.
12.2.7 Offset 0Dh: PMLT—Primary Master Latency Timer
This register does not apply to PCI Express*, and is maintained as R/W for software compatibility.
12.2.8 Offset 0Eh: HEADTYP—Header Type
This register determines how the rest of the configuration space is laid out.
Table 39. Offset 09h: CC—Class Code
Bits Type Reset Description
23:16 RO 06h Base Class Code (BCC): The value of 06h indicates that this is a bridge device.
15:8 RO 04h Sub Class Code (SCC): This 8-bit value indicates that this device is a PCI-to-PCI Bridge.
7:0 RO 00h Programming Interface (PIF): This bit indicates that this d evice is standard (non-
subtractive) PCI-to-PCI Bridge.
Table 40. Offset 0Ch: CLS—Cache Line Size
Bits Type Reset Description
7:0 RW 00h
Cache Line Size (CLS): These bits specify the system cache-line size in units of Dwords:
• 08h: 32-byte line (8 DWords)
• 10h 64-byte line
• 20h 128-byte line
Any value outside this range defaults to a 64-byte line. When creating read requests to PCI
Express*, this value is used to partition speculative PCI read requests on cache-line–
aligned boundaries. This register has no other effect on the 41210.
Table 41. Offset 0Dh: PMLT—Primary Master Latency Timer
Bits Type Reset Description
7:3 RO 00h Time Value (TV): Not applicable for PCI Express*
2:0 RO 000b Reserved
Table 42. Offset 0Eh: HEADTYP—Header Type
Bits Type Reset Description
7RO 1b
Multi-function device (MFD): Reserved as 1 to indicate that the 41210 is a multi-function
device.
6:0 RO 01h Header Type (HTYPE): These bits define the layout of addresses 10h through 3Fh in the
configuration space. These bits read as 01h to indicate that the register layout conforms to
the standard PCI-to-PCI Bridge layout.