1270 | Intel 41210 manual

12.2.58Offset 11C–12Bh: HDR_LOG—PCI Express* Transaction Header Log

This register is the transaction header log for PCI Express* errors.

Table 92.	Offset 11C–12Bh: HDR_LOG—PCI Express* Transaction Header Log

Bits	Type	Reset	Description

127:0	ROS	0	Header of the PCI Express* Packet in Error: As soon as an error is logged in this register,
127:0	ROS	0	it remains locked for further error-logging until the software clears the status bit that caused
			the header log (in other words, until the error pointer is re-armed for logging again).

110	Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

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Image 110

Intel 41210 manual Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log, 1270

Contents

Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Revision History Date Revision Description Introduction1 PCI Express* Interface FeaturesPCI-X Interface Features Jtag Power ManagementSMBus Interface Signal Description On-Die Termination ODT ADEVSEL# BDEVSEL# AFRAME# BFRAME# ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 AGNT#50 BGNT#50 PERCOMP10 PCI Express* Interface PinsPCI Express* Interface Total ADEVSEL# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances AIRDY# PCI Interface Pins Sheet 2 PCI Bus Interface 64-Bit Extension Two Interfaces PCI Interface Pins 64-Bit ExtensionsPCI Clock and Reset Pins AINTA# AINTB# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTC# AINTD# Cfgretry Reset StrapsReset Strap Pins SMBus Interface Pins Miscellaneous Pins Miscellaneous Pins Voltage Pins Number Description This page Intentionally Left Blank Initialization PCI Mode Pin/Strap EncodingPCI-X Interface PCI-X Initialization Pattern PCI Transactions Supported PCI ModeTransactions Supported Transaction Encoding1 PCI-X Transactions Supported PCI-X ModeRead Transactions Configuration Transactions Delayed PCI Lock CyclesEnd Point Source Decoding Transaction Termination PCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface 2 4 GB and 4 K Page Crossover PCI-X Protocol SpecificsAttributes Wait States Fields ArbitrationSplit Transactions Split Completion Abort Registers Internal Arbitration Scheme BridgeM0 High Priority Group Lpg Low Priority B3173-01 Software-Driven PCI-PM 1.1-Compatible Power Management Power ManagementHardware-Controlled Active State Power Management PCI Bus Power Management Power-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge B Configuration Space Addressable Space AccessPCI-to-PCI Bridge a Configuration Space Addressing5 Device Number Signal Used for Public/Private Configuration-Space AccessPCI Express* Configuration Access Secondary PCI Devices Addressing Type 0 Configuration Access from PCI-X Interface Type 1 to Type 0 Translation PCI and PCI-X I/O Space Access Mechanism SMBus Configuration Access O Forwarding Memory Space Access Mechanism Memory-Mapped I/O Window Memory Forwarding Opaque Memory Window VGA AddressingPrefetchable Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass Column Downstream Transaction Ordering Downstream Transaction OrderingRelaxed Ordering/No-Snoop Support INTx Routing Table Interrupt SupportLegacy Interrupt Sharing Device Number on Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Secondary Bus Bit Value System Management Bus InterfaceSMBus Address Assignments Internal Command SMBus CommandsSMBus Command Encoding SMBus command SMBus Status Byte Encoding ConfigurationInitialization Sequence Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clocking Clock and ResetDevice Reset Clock Domains PCI Express* Reset Mechanism PERST# Reset MechanismRSTIN# Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Errors Error HandlingPCI Express* Errors Completion-Status Translation for Immediate Terminations Error TypesTermination of Completion Required Transactions PCI-X Termination PCI Express* Completion Successful 00h PCI-X Split Termination Message PCI ExpressIndex Split Termination on PCI Express* Interface PCI Express* Completion Status PCI Completion Register Description Register Nomenclature and Access AttributesPERST# reset Bit Attribute Definitions Configuration Registers 0xFFF 0x300 0x100 0x40 0x00 PCI/PCI-X Compatible Configuration regionCapptr B3174-02 Legacy Configuration Space Byte Offset PCI Express* Extended Configuration SpaceRegister Reset Description Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Offset 00h ID-Identifiers Offset 06h PSTS-Primary Device Status Sheet 1 Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Type Offset 08h REVID-Revision ID Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 Bits Offset 0Ch CLS-Cache-Line Size Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Eh HEADTYP-Header Type Offset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus Numbers FFFh Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit Support for 16-bit I/O addressing only Offset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status 3120 000h Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit Must be less than this value Offset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 24h PMBL-Prefetchable Memory Base and Limit Offset 34h CAPP-Capabilities List Pointer Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 3Ch INTR-Interrupt Information Offset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge Control Sheet 2 Peer Memory Read Enable Pmre Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Bit Maximum Number of Upstream Delayed Transactions Offset 44h EXPCAPID-PCI Express* Capability Identifier Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 45h EXPNXTP-Next Item Pointer Offset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxPayloadSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxReadRequestSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit Latency Offset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Eh PMPMC-Power Management Capabilities Offset 73h PMDATA-Power Management Data Field Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 72h PMBSE-Power Management Bridge Support Extensions Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D9h PXNXTP-PCI-X Next Item Pointer Offset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary Status Offset DCh PXBSTS-PCI-X Bridge Status Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization Register ID, indicating Advanced Error Reporting Capability Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number When the configuration unit signals a completer abort Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Data Link Protocol Error Severity Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Training Error Severity Not supported Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask 1270 Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header LogOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Sheet 1 Sheet 2 Logs the header PCI-X Uncorrectable Address Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Attribute Parity Error Detected Mask PCI-X Detected Target Abort Mask optional in specification PCI-X Detected Split Completion Master Abort Mask PCI-X Uncorrectable Address Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Data Parity Error Detected Severity Register is cleared by the software writing a 1 to the bit Rwcs = Errnonfatal = ErrfatalPCI-X Detected Split Completion Master Abort Severity Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Reserved Read only Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register SMBUS5 SMBUS3 SMBUS2 SMBUS1 6360 RsvdP Offset 178h PREFCTRL-Prefetch Control RegisterOffset 178h PREFCTRL-Prefetch Control Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 308h PWRBGTDATA-Power Budgeting Data Register

12.2.58Offset 11C–12Bh: HDR_LOG—PCI Express* Transaction Header Log

Offset 11C–12Bh: HDR_LOG—PCI Express* Transaction Header Log

127:0

ROS

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual