Intel 41210 guide

Register Description

12.2.56Offset 114h: ERRCOR_MSK—PCI Express* Correctable Error Mask

This register controls the reporting of individual correctable errors via ERR_COR message. A masked error (respective bit set in mask register) is not reported to the host bridge by the 41210. There is a mask bit corresponding to every bit in the Correctable Error Status Register (Offset 110h: ERRCOR_STS—PCI Express* Correctable Error Status).

Table 90.		Offset 114h: ERRCOR_MSK—PCI Express* Correctable Error Mask

Bits		Type	Reset		Description

31:13		RsvdP	0	Preserved

				Replay Timer Time-out Mask:
12		RWS	0b	0 =	Not masked
				1 =	Masked

11:9		RsvdP	000b	Preserved

				Replay Number Rollover Mask:
8		RWS	0b	0 =	Not masked
				1 =	Masked

				Bad DLLP Mask:
7		RWS	0b	0 =	Not masked
				1 =	Masked

				Bad TLP Mask:
6		RWS	0b	0 =	Not masked
				1 =	Masked

5:1		RsvdP	0 0000b	Preserved

				Receiver Error Mask:
0		RWS	0b	0 =	Not masked
				1 =	Masked

12.2.57Offset 118h: ADVERR_CTL—Advanced Error Control and Capability Register

This register gives the status and control for ECRC checks and also the pointer to the first uncorrectable error that happened.

Table 91.		Offset 118h: ADVERR_CTL—Advanced Error Control and Capability Register

Bits		Type	Reset	Description

31:9		RsvdP	0	Preserved

8		RO	0b	ECRC Check Enable: Not supported—hard-wired to 0

7		RO	0b	ECRC Check Capable: Not supported—hard-wired to 0

6		RO	0b	ECRC Generation Enable: Not supported—hard-wired to 0

5		RO	0b	ECRC Generation Capable: Not supported—hard-wired to 0

				The First Error Pointer: This field identifies the bit position of the first error reported in the
4:0		ROS	0 0000b	Uncorrectable Error Status Register (“Offset 104h: ERRUNC_STS—PCI Express*
4:0		ROS	0 0000b	Uncorrectable Error Status Register” on page 105). This register re-arms itself (which does
				not change its current value) as soon as the error status bit indicated by the pointer is
				cleared by the software by writing a 1 to that status bit.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

109

Image 109

Intel 41210 manual Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask

Contents

Developer’s Manual Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision History PCI-X Interface Features PCI Express* Interface FeaturesIntroduction1 SMBus Interface Power ManagementJtag On-Die Termination ODT Signal Description AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ODT SignalsADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50 PCI Express* Interface PCI Express* Interface PinsPERCOMP10 Total PCI Bus Interface Two Instances PCI Interface Pins Sheet 1ADEVSEL# AIRDY# PCI Interface Pins Sheet 2 PCI Clock and Reset Pins PCI Interface Pins 64-Bit ExtensionsPCI Bus Interface 64-Bit Extension Two Interfaces Interrupt Interface Two Interfaces Interrupt Interface PinsAINTA# AINTB# AINTC# AINTD# Reset Strap Pins Reset StrapsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous Pins Number Description Voltage Pins This page Intentionally Left Blank PCI-X Interface PCI Mode Pin/Strap EncodingInitialization PCI-X Initialization Pattern Transactions Supported PCI ModePCI Transactions Supported Transaction Encoding1 Read Transactions PCI-X ModePCI-X Transactions Supported Delayed Configuration Transactions End Point Source Lock CyclesPCI Transaction Termination Decoding PCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Attributes PCI-X Protocol Specifics2 4 GB and 4 K Page Crossover Wait States Split Transactions ArbitrationFields Split Completion Abort Registers BridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration Scheme Hardware-Controlled Active State Power Management Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power Management Power-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge a Configuration Space Addressable Space AccessPCI-to-PCI Bridge B Configuration Space Addressing5 PCI Express* Configuration Access Configuration-Space AccessDevice Number Signal Used for Public/Private Secondary PCI Devices Addressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X Interface SMBus Configuration Access I/O Space Access Mechanism O Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O Window Prefetchable Memory Window VGA AddressingOpaque Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass Column Relaxed Ordering/No-Snoop Support Downstream Transaction OrderingDownstream Transaction Ordering Legacy Interrupt Sharing Interrupt SupportINTx Routing Table Interrupt Binding for Devices behind a Bridge Interrupt Routing for Devices behind a BridgeDevice Number on Secondary Bus SMBus Address Assignments System Management Bus InterfaceBit Value SMBus Command Encoding SMBus CommandsInternal Command SMBus command Initialization Sequence ConfigurationSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Device Reset Clock and ResetClocking Clock Domains RSTIN# Reset Mechanism PERST# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Express* Errors Error HandlingPCI Errors Termination of Completion Required Transactions Error TypesCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* Completion Index PCI-X Split Termination Message PCI ExpressSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* Interface PERST# reset Register Nomenclature and Access AttributesRegister Description Bit Attribute Definitions Configuration Registers Capptr PCI/PCI-X Compatible Configuration region0xFFF 0x300 0x100 0x40 0x00 B3174-02 Legacy Configuration Space Register PCI Express* Extended Configuration SpaceByte Offset Offset 04h PCICMD-Command Register Sheet 1 Offset 04h PCICMD-Command RegisterReset Description Offset 00h ID-Identifiers Offset 06h PSTS-Primary Device Status Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Sheet 1 Type Offset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 08h REVID-Revision ID Bits Offset 09h CC-Class Code Offset 0Dh PMLT-Primary Master Latency TimerOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header Type Offset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus Numbers Offset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing only Offset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status Offset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this value Offset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and Limit Offset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt Information Offset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed Transactions Offset 43h PCLKC-PCI Clock Control Offset 42h MTT-Multi-Transaction TimerOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item Pointer Offset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxReadRequestSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxPayloadSize Offset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit Latency Offset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 5Eh MSIMC-PCI Express* MSI Message Control Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management Capabilities Offset 72h PMBSE-Power Management Bridge Support Extensions Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item Pointer Offset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization Register Advanced Error Reporting Extended Capability Version Number Power Budgeting Capability as the next capabilityID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abort Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Flow Control Protocol Error Status Severity Unsupported Request Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supported Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2 PCI Delayed Transaction Timer Expiry Mask Internal Bridge Data Error MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected Mask PCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specification PCI Delayed Transaction Timer Expiry Severity Internal Bridge Data Error SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected Severity PCI-X Detected Split Completion Master Abort Severity Rwcs = Errnonfatal = ErrfatalRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS1 Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register