Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 21

Signal Description
2.8 SMBus Interface

Table 8. SMBus Interface Pins

Signal I/O Description
SMBCLK I/OD SMBus Clock: This signal must be pulled to 3.3 V through an 8.2 KΩ resistor.
SMBDAT I/OD SMBus Data: This signal must be pulled to 3.3V through an 8.2 KΩ resistor.
SMBUS[5]
SMBUS[3:1] I
SMBus Addressing Straps: These straps set the SMBus address for the 41210 Bridge. The address
is determined as indicated below:
•Bit[7]1
•Bit[6]1
• Bit[5] SMBUS[5]
•Bit[4]0
• Bit[3] SMBUS[3]
• Bit[2] SMBUS[2]
• Bit[1] SMBUS[1]
These signals (bits[5], [3:1]) must be pulled up to 3.3V or down to ground. S ampled at the rising edge
of PERST#.
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