Signal Description
2.9Miscellaneous Pins
Table 9. | Miscellaneous Pins |
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| Signal |
| I/O |
| Description |
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| Configuration Reset: This signal is asserted low when ever the bridge goes |
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| through a fundemental reset (PERST#, RSTIN#, or PCI Express Reset). This |
| CFGRST# |
| O |
| signal should be used to indicate when the local initialization methods should be |
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| executed. | ||
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| Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more |
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| information. |
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| PERST# |
| I |
| PCI Express Fundamental Reset: When low, asynchronously resets the |
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| internal logic (including sticky bits). | ||
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| Reset In: When Asserted, this signal asynchronously resets the internal logic |
| RSTIN# |
| I |
| and asserts X_RST# output for both PCI interfaces. This signal should be pulled |
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| high for adapter card usage. |
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| TAP Clock In: This is the input clock to the JTAG TAP controller. Acceptable |
| TCK |
| I |
| frequency is |
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| If not utilizing JTAG, this signal can be left as a no connect. |
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| Test Data In: This is the serial data input to the JTAG BSCAN shift register |
| TDI |
| I |
| chain and to the JTAG BSCAN control logic. This is latched in on the rising edge |
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| of TCK. | ||
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| If not utilizing JTAG, this signal can be left as a no connect. |
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| TDO |
| O |
| Test Data Output: This is the serial data output from the JTAG BSCAN logic |
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| If not utilizing JTAG, this signal can be left as a no connect. | ||
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| Test Mode Select: This signal controls the TAP controller state machine to |
| TMS |
| I |
| move to different states and is sampled on the rising edge of TCK. |
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| If not utilizing JTAG, this signal can be left as a no connect. |
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| Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN |
| TRST# |
| I |
| logic. |
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| If not utilizing JTAG, connect this signal to ground through a 1KΩ | ||
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| resistor. |
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| RESERVED[8:1] |
| I |
| Reserved: (8 pins) These input pins should be pulled low |
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| Use an approximately 8.2KΩ resistor to | ||
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| NC[19:18], NC[16:1] |
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| No Connect: (39 pins) These output pins should be left floating |
| A_NC[10:1] |
| O |
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| B_NC[10:1] |
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| NC[17] |
| O |
| This signal requires an external |
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| Total |
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22 | Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual |
