Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 107

Register Description
12.2.54 Offset 10Ch: ERRUNC_SEV—PCI Express* Uncorrectable Error Severity

This register controls whether an individual uncorrectable error is reported as a fatal error. An

uncorrectable error is reported as fatal when the corresponding error bit in this register is set. When

the bit is cleared, the corresponding error is considered non-fatal.

Table 88. Offset 10Ch: ERRUNC_SEV—PCI Express* Uncorrectable Error Severity

Bits Type Reset Description
31:21 RsvdP 000h Preserved
20 RWCS 0b
Unsupported Request Error Status Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
19 RO 0b ECRC Check Severity: Not supported
18 RWCS 0b
Malformed TLP Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
17 RWCS 0b
Receiver Overflow Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
16 RWCS 0b
Unexpected Completion Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
15 RWCS 0b
Completer Abort Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
14 RWCS 0b
Completion Time Out Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
13 RWCS 0b
Flow Control Protocol Error Status Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
12 RWCS 0b
Poisoned TLP Received Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
11:5 RsvdP 00h Preserved
4RWCS 0b
Data Link Protocol Error Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
3:1 RsvdP 000b Preserved
0RO 0b
Training Error Severity: Not supported