Register Description

 

Table 93.

Offset 12Ch: PCIXERRUNC_STS—Uncorrectable PCI-X Status Register

 

 

(Sheet 2 of 2)

 

 

 

 

 

 

Bits

 

Type

Reset

Description

 

 

 

 

 

 

 

 

 

PCI-X Detected Target Abort (optional in specification): The 41210 sets this bit when it

2

 

RWCS

0b

is the master of a request transaction on the PCI bus and it receives a target abort. The

 

41210 logs the header for that transaction. This bit is also set when the bridge receives a

 

 

 

 

PCI-X Split Completion Message with Target Abort Status. The header log under this

 

 

 

 

condition is the command, address, and attribute portion of the Split Completion Message.

 

 

 

 

 

 

 

 

 

PCI-X Detected Split Completion Master Abort: The 41210 sets this bit when a split

1

 

RWCS

0b

completion sent by the 41210 on the PCI-X bus master-aborts. The 41210 logs the header

 

 

 

 

of the split completion.

 

 

 

 

 

 

 

 

 

PCI-X Detected Split Completion Target Abort (optional in specification): The 41210

0

 

RWCS

0b

sets this bit when a split completion sent by the 41210 on the PCI-X bus target-aborts. The

 

 

 

 

41210 logs the header.

 

 

 

 

 

112

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Page 112
Image 112
Intel 41210 manual Sheet 2, Logs the header