Offset 30h IOBLU16-I/O Base and Limit Upper 16 Bits | Intel 41210

Register Description

12.2.16Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits

This register defines the upper 32 bits of the prefetchable address base register.

Table 50. Offset 2Ch: PMLU32—Prefetchable Memory Limit Upper 32 Bits

Bits	Type	Reset	Description

31:0	RW	0000 0000h	Prefetchable Memory Limit Upper Portion (PMLU): These bits indicate that full 64-bit
			addressing is supported.

12.2.17Offset 30h: IOBLU16—I/O Base and Limit Upper 16 Bits

Since I/O is limited to 64 KB, this register is reserved and not used.

Table 51.		Offset 30h: IOBLU16—I/O Base and Limit Upper 16 Bits

Bits		Type	Reset		Description

31:16		RO	0000h	I/O Base High 16	Bits (IOBH): Reserved

15:0		RO	0000h	I/O Limit High 16	Bits (IOLH): Reserved

12.2.18Offset 34h: CAPP—Capabilities List Pointer

This register contains the pointer for the first entry in the capabilities list.

Table 52.		Offset 34h: CAPP—Capabilities List Pointer

Bits		Type	Reset	Description

7:0		RO	44h	Capabilities Pointer (PTR): These bits indicate that the pointer for the first entry in the
7:0		RO	44h	capabilities list is at 44h (PCI Express* capability) in the configuration space.

12.2.19Offset 3Ch: INTR—Interrupt Information

This register contains information on interrupts on the bridge.

Table 53.		Offset 3Ch: INTR—Interrupt Information

Bits		Type	Reset	Description

15:8		RO	00h	Interrupt Pin (PIN): These bits indicate that no interrupt is used by the bridge segment.

7:0		RW	00h	Interrupt Line (LINE): This register is used to convey the interrupt line routing information
7:0		RW	00h	between the initialization code and the device driver.
				between the initialization code and the device driver.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

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Image 87

Intel 41210 Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 Bits, Offset 30h IOBLU16-I/O Base and Limit Upper 16 Bits

Contents

Developer’s Manual Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision History PCI Express* Interface Features PCI-X Interface FeaturesIntroduction1 Power Management SMBus InterfaceJtag On-Die Termination ODT Signal Description AGNT#50 BGNT#50 ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ADEVSEL# BDEVSEL# AFRAME# BFRAME# Total PCI Express* Interface PinsPCI Express* Interface PERCOMP10 AIRDY# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances ADEVSEL# PCI Interface Pins Sheet 2 PCI Interface Pins 64-Bit Extensions PCI Clock and Reset PinsPCI Bus Interface 64-Bit Extension Two Interfaces AINTC# AINTD# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTA# AINTB# Reset Straps Reset Strap PinsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous Pins Number Description Voltage Pins This page Intentionally Left Blank PCI-X Initialization Pattern PCI Mode Pin/Strap EncodingPCI-X Interface Initialization Transaction Encoding1 PCI ModeTransactions Supported PCI Transactions Supported PCI-X Mode Read TransactionsPCI-X Transactions Supported Delayed Configuration Transactions Lock Cycles End Point SourcePCI Transaction Termination Decoding PCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Wait States PCI-X Protocol SpecificsAttributes 2 4 GB and 4 K Page Crossover Split Completion Abort Registers ArbitrationSplit Transactions Fields BridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration Scheme PCI Bus Power Management Power ManagementHardware-Controlled Active State Power Management Software-Driven PCI-PM 1.1-Compatible Power Management Power-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressing5 Addressable Space AccessPCI-to-PCI Bridge a Configuration Space PCI-to-PCI Bridge B Configuration Space Secondary PCI Devices Configuration-Space AccessPCI Express* Configuration Access Device Number Signal Used for Public/Private Addressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X Interface SMBus Configuration Access I/O Space Access Mechanism O Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O Window VGA Addressing Prefetchable Memory WindowOpaque Memory Window § § Row Pass Column Transaction OrderingUpstream Transaction Ordering Upstream Transaction Ordering Downstream Transaction Ordering Relaxed Ordering/No-Snoop SupportDownstream Transaction Ordering Interrupt Support Legacy Interrupt SharingINTx Routing Table Secondary Bus Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Device Number on System Management Bus Interface SMBus Address AssignmentsBit Value SMBus command SMBus CommandsSMBus Command Encoding Internal Command Configuration Initialization SequenceSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock Domains Clock and ResetDevice Reset Clocking PERST# Reset Mechanism RSTIN# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank Error Handling PCI Express* ErrorsPCI Errors PCI-X Termination PCI Express* Completion Error TypesTermination of Completion Required Transactions Completion-Status Translation for Immediate Terminations PCI-X Split Termination Message PCI Express IndexSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* Interface Bit Attribute Definitions Register Nomenclature and Access AttributesPERST# reset Register Description Configuration Registers B3174-02 PCI/PCI-X Compatible Configuration regionCapptr 0xFFF 0x300 0x100 0x40 0x00 Legacy Configuration Space PCI Express* Extended Configuration Space RegisterByte Offset Offset 00h ID-Identifiers Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Reset Description Type Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Offset 06h PSTS-Primary Device Status Sheet 1 Bits Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision ID Offset 0Eh HEADTYP-Header Type Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Ch CLS-Cache-Line Size Offset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus Numbers Support for 16-bit I/O addressing only Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit FFFh Offset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status Must be less than this value Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit 3120 000h Offset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 3Ch INTR-Interrupt Information Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 34h CAPP-Capabilities List Pointer Offset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 2 Bit Maximum Number of Upstream Delayed Transactions Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Peer Memory Read Enable Pmre Offset 45h EXPNXTP-Next Item Pointer Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 44h EXPCAPID-PCI Express* Capability Identifier Default Description Offset 46h EXPCAP-PCI Express* CapabilityOffset 46h EXPCAP-PCI Express* Capability Offset 4Ch EXPDCTL-PCI Express* Device Control Register Bit MaxReadRequestSizeBit MaxPayloadSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 50h EXPLCAP-PCI Express* Link Capabilities RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register L0s Exit Latency Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register Offset 54h EXPLCTL-PCI Express* Link Control Register Offset 56h EXPLSTS-PCI Express* Link Status Register Offset 5Ch MSICAPID-PCI Express* MSI Capability IdentifierOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item Pointer Offset 70h PMPMCSR-Power Management Control/Status Register Offset 72h PMBSE-Power Management Bridge Support ExtensionsOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge Status Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization Register When the configuration unit signals a completer abort Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number ID, indicating Advanced Error Reporting Capability Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Training Error Severity Not supported Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Data Link Protocol Error Severity Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2 PCI-X Uncorrectable Attribute Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specification PCI-X Uncorrectable Data Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Address Parity Error Detected Severity Rwcs = Errnonfatal = Errfatal PCI-X Detected Split Completion Master Abort SeverityRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log SMBUS5 SMBUS3 SMBUS2 SMBUS1 Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register Reserved Read only Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register