Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 113

Register Description
12.2.60 Offset 130h: PCIXERRUNC_MSK—UncorrectablePCI-X Error Mask Register

This register masks the reporting of PCI-X uncorrectable errors. There is one mask bit per error.

Note that the status bits are set in the status register regardless of whether the mask bit is on or off.

The mask bit also affects the header log for the PCI-X transaction. When the mask bit is on, the

header is not logged and no error message is generated on PCI Express*.

Table 94. Offset 130h: PCIXERRUNC_MSK—Uncorrectable PCI-X Error Mask Register

(Sheet 1 of 2)
Bits Type Reset Description
15:14 RsvdP 00b Preserved
13 RWCS 0b
Internal Bridge Data Error Mask:
0 = Not masked
1 = Masked
12 RWCS 0b
PCI-X SERR# Detected Mask:
0 = Not masked
1 = Masked
11 RWCS 0b
PCI-X PERR# Detected Mask:
0 = Not masked
1 = Masked
10 RWCS 0b
PCI Delayed Transaction Timer Expiry Mask:
0 = Not masked
1 = Masked
9RWCS 0b
PCI-X Uncorrectable Address Parity Error Detected Mask:
0 = Not masked
1 = Masked
8RWCS 0b
PCI-X Uncorrectable Attribute Parity Error Detected Mask:
0 = Not masked
1 = Masked
7RWCS 0b
PCI-X Uncorrectable Data Parity Error Detected Mask:
0 = Not masked
1 = Masked
6RWCS 0bSplit Completion Message Data Error Mask
5RWS 1b
Unexpected Split Completion Error Mask
4 RsvdP 0b Preserved
3RWCS 0b
PCI-X Detected Master Abort Mask:
0 = Not masked
1 = Masked