Register Description

12.2.60Offset 130h: PCIXERRUNC_MSK—Uncorrectable PCI-X Error Mask Register

This register masks the reporting of PCI-X uncorrectable errors. There is one mask bit per error. Note that the status bits are set in the status register regardless of whether the mask bit is on or off. The mask bit also affects the header log for the PCI-X transaction. When the mask bit is on, the header is not logged and no error message is generated on PCI Express*.

Table 94. Offset 130h: PCIXERRUNC_MSK—Uncorrectable PCI-X Error Mask Register (Sheet 1 of 2)

Bits

Type

Reset

 

Description

 

 

 

 

15:14

RsvdP

00b

Preserved

 

 

 

 

 

 

 

Internal Bridge Data Error Mask:

13

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

 

 

PCI-X SERR# Detected Mask:

12

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

 

 

PCI-X PERR# Detected Mask:

11

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

 

 

PCI Delayed Transaction Timer Expiry Mask:

10

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

 

 

PCI-X Uncorrectable Address Parity Error Detected Mask:

9

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

 

 

PCI-X Uncorrectable Attribute Parity Error Detected Mask:

8

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

 

 

PCI-X Uncorrectable Data Parity Error Detected Mask:

7

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

6

RWCS

0b

Split Completion Message Data Error Mask

 

 

 

 

5

RWS

1b

Unexpected Split Completion Error Mask

 

 

 

 

4

RsvdP

0b

Preserved

 

 

 

 

 

 

 

PCI-X Detected Master Abort Mask:

3

RWCS

0b

0 =

Not masked

 

 

 

1 =

Masked

 

 

 

 

 

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

113

Page 113
Image 113
Intel 41210 manual Internal Bridge Data Error Mask, PCI-X SERR# Detected Mask, PCI-X PERR# Detected Mask