Intel 41210 manual Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask

Register Description

12.2.53Offset 108h: ERRUNC_MSK—PCI Express* Uncorrectable Error Mask

This register controls the reporting of individual uncorrectable errors by device to the host bridge via a PCI Express* error message. This register also controls the logging of the header. Refer to the PCI Express* specifications for details of how the mask bits function. A masked error (respective bit set in the mask register) is not reported to the host bridge by the 41210, nor is the header logged (status bits unaffected by the mask bit). There is a mask bit per bit of the Uncorrectable Error Status Register (“Offset 104h: ERRUNC_STS—PCI Express* Uncorrectable Error Status Register” on page 105).

Table 87.	Offset 108h: ERRUNC_MSK—PCI Express* Uncorrectable Error Mask
Bits	Type	Reset		Description
31:21	RsvdP	000h	Preserved
			Unsupported Request Error Status Error Mask:
20	RWCS	0b	0 =	Not masked
			1 =	Masked
19	RO	0b	ECRC Check Error Mask: Not supported
			Malformed TLP Error Mask:
18	RWCS	0b	0 =	Not masked
			1 =	Masked
			Receiver Overflow Error Mask:
17	RWCS	0b	0 =	Not masked
			1 =	Masked
			Unexpected Completion Error Mask:
16	RWCS	0b	0 =	Not masked
			1 =	Masked
			Completer Abort Error Mask:
15	RWCS	0b	0 =	Not masked
			1 =	Masked
			Completion Time Out Error Mask:
14	RWCS	0b	0 =	Not masked
			1 =	Masked
			Flow Control Protocol Error Status Error Mask:
13	RWCS	0b	0 =	Not masked
			1 =	Masked
			Poisoned TLP Received Error Mask:
12	RWCS	0b	0 =	Not masked
			1 =	Masked
11:5	RsvdP	00h	Preserved
			Data Link Protocol Error Mask:
4	RWCS	0b	0 =	Not masked
			1 =	Masked
3:1	RsvdP	000b	Preserved
0	RO	0b	Training Error Mask: Not supported

106 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual