Intel 41210 manual Local Initialization

	Local Initialization
Local Initialization	9

The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) includes device-specific registers that allow for control of the bridges’s behavior, both internally and externally. Examples of these device-specific registers are the arbiter control register, the prefetch control register, and so on. Depending on the usage model, these registers might need to be programmed to a different value than the reset-default, every time 41210 goes through a component reset.

When application-specific initialization of the 41210 is required, the CFGRETRY strap must be asserted at the rising edge of PERST#. This places the 41210 Bridge in a local initialization mode, and all configuration accesses from PCI Express* is retried by returning a completion with the configuration request retry status. As soon as the local configuration is completed, the “Local Initialization In Progress bit” in the “Offset FCh: BINIT—Bridge Initialization Register” on page 104 must be cleared to enable host access to the bridge configuration registers.

Local initialization can be accomplished via SMBus access or Type 0 configuration cycles from the secondary bus. The CFGRST# output is asserted whenever the configuration space is reset and can be used as a control signal to re-initialize the application-specific parameters. The X_RST# signal must not be used since the configuration space is not cleared due to a software-initiated secondary bus reset.

Device-specific registers are listed below:

•“Offset 40h: BCNF—Bridge Configuration Register” on page 90

•“Offset 42h: MTT—Multi-Transaction Timer” on page 91

•“Offset 43h: PCLKC—PCI Clock Control” on page 91

•“Offset FCh: BINIT—Bridge Initialization Register” on page 104

•“Offset 16Ah: ARB_CNTRL—Internal Arbiter Control Register” on page 117

•“Offset 170h: SSR—Strap Status Register” on page 118

•“Offset 178h: PREFCTRL—Prefetch Control Register” on page 119

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Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 63