Intel 41210 manual Error Handling, PCI Express* Errors, PCI Errors

	Error Handling
Error Handling	11

For each interface, the Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) implements the specified error-logging and escalation actions as per the interface rules. For example, errors encountered on the PCI interface follow the logging and escalation rules of PCI. The error escalation mechanisms implemented by the 41210 can be fully masked. This feature provides the platform software with the ability to pick and choose what it wants to do on any of the error conditions. All logging registers specific to the 41210 are “sticky” (these registers retain their values) through any chip reset except a PERST# reset cycle.

11.1PCI Express* Errors

The 41210 supports the PCI Express* advanced error-reporting capability, which allows for system-level error recovery and debugging. The capability includes both the base error-reporting features and the bridge-specific extensions for reporting PCI and PCI-X errors.

PCI Express* errors are classified as either correctable errors or uncorrectable errors:

•Correctable errors are those for which hardware exists to correct the errors.

•Uncorrectable errors are errors for which hardware does not exist to correct the errors.

Uncorrectable errors are further classified into fatal and non-fatal errors, with non-fatal errors indicating an unreliable link.

PCI Express* supports three different error messages to support these error classes: ERR_COR, ERR_UNC and ERR_FATAL. Refer to the PCI Express* Specification, Revision 1.0a for details of the various PCI Express* errors and how they are signaled and escalated.

PCI Express* error logging specifies a set of advanced transaction-logging registers as an added capability.

11.2PCI Errors

PCI and PCI-X errors include several sources of error, such as the following:

•Address errors

•Data-parity errors

•Split-completion errors

•Master aborts

•Target aborts

Some of these errors are fatal and some are non-fatal. The PCI-X specifications specify a set of rules for the behavior of a bridge under a variety of error conditions that could happen on the bus. To aid the system software/driver in error recovery and debugging, the 41210 implements those rules on PCI along with the error-logging and routing control specific to the 41210.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 69