116 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
Register Description
12.2.62 Offset 138h: PCIXERRUNC_PTR—UncorrectablePCI-X Error Pointer
This register points to the first error that occurred. This register is re-armed when the error status
register corresponding to the error indicated by this register is cleared by the software writing a 1 to
the bit.
2RWCS 0b
PCI-X Detected Target Abort Severity: (optional in specification)
0 = ERR_NONFATAL
1 = ERR_FATAL
1RWCS 0b
PCI-X Detected Split Completion Master Abort Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
0RWCS 0b
PCI-X Detected Split Completion Target Abort Severity: (optional in specification)
0 = ERR_NONFATAL
1 = ERR_FATAL
Table 95. Offset 130h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register
(Sheet 2 of 2)
Bits Type Reset Description
Table 96. Offset 138h: PCIXERRUNC_PTR—Uncorrectable PCI-X Error Pointer Register
Bits Type Reset Description
15:4 RsvdP 000h Preserved
3:0 ROS 0h
PCI First Error Pointer: This register points to the first error that is logged in the status
register (as long as the corresponding mask bit is clear and the pointer is re-armed). This
register re-arms itself when the status bit corresponding to the error indicated by this
register is cleared by the software writing a 1 to the bit.