78 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Register Description
12.2.1 Offset 00h: ID—Identifiers

Contains the vendor and device identifiers for software.

12.2.2 Offset 04h: PCICMD—Command Register

This register controls how the device behaves on the primary interface (PCI Express*). As this

component is a bridge, additional command information is located in a separate Bridge Control

register (“Offset 3Eh: BCTRL—Bridge Control” on page88).

Table 35. Offset 00h: ID—Identifiers

Bits Type Reset Description
31:16 RO AB
Device ID (DID): These bits indicate the device number assigned by Intel to the Intel®
41210 Serial to Parallel PCI Bridge.
0340h 0341h
15:0 RO 8086h Vendor ID (VID): This 16-bit field indicates that Intel is the vendor.

Table 36. Offset 04h: PCICMD—Command Register (Sheet 1 of 2)

Bits Type Reset Description
15:11 RO 00h Reserved
10 RW 0b INTx Mask: The bridge does not generate internal interrupts. The value of this bit has no
meaning.
9RO 0b
Fast Back-to-back enable (FBE): This bit has no meaning on PCI Express*.
This bit must be hard-wired to 0.
8RW 0b
SERR# Enable (SEE): This bit enables reporting of non-fatal and fatal errors to the root
complex.
0 = Disable reporting errors
1 = Enable reporting of non-fatal and fatal errors to the root complex
NOTE: Errors are reported when enabled either through this bit or through the PCI
Express*-specific bits in the Device Control Register (“Offset 4Ch: EXP_DCTL—
PCI Express* Device Control Register” on page 93).
7RO 0b
Wait Cycle Control (WCC): Reserved
6RW 0b
Parity Error Response Enable (PERE): This bit controls the setting of the master data
parity error bit in the Status Register (“Offset 06h: PSTS—Primary Device Status” on
page 79) in response to a parity error received on the PCI Express* interface (poisoned
TLP) or peer PCI interface.
0 = The 41210 ignores these errors on the PCI Express*/peer-PCI interface.
1 = The 41210 reports read completion data parity errors on PCI Express* and sets the
MDPD bit in the status register.
5RO 0b
VGA Palette Snoop Enable (VGA_PSE): Reserved
4RO 0b
Memory Write and Invalidate Enable (MWIE): Memory write and invalidate transactions
are not generated, since PCI Express* does not have a corresponding transfer type.
3RO 0b
Special Cycle Enable (SCE): Reserved