Internal Bridge Data Error Severity | Intel 41210 manual

Register Description

12.2.61Offset 134h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register

This register controls the severity of the reporting of PCI-X uncorrectable errors. There is one mask bit per error. When a bit is set to 1, the corresponding error, when enabled, generates an ERR_FATAL message on PCI Express*. When a bit is cleared to 0, the corresponding error, when enabled, causes a ERR_NONFATAL on PCI Express*.

Table 95. Offset 130h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register (Sheet 1 of 2)

Bits	Type	Reset		Description

15:14	RsvdP	00b	Preserved

			Internal Bridge Data Error Severity:
13	RWCS	0b	0 =	ERR_NONFATAL
			1 =	ERR_FATAL

			PCI-X SERR# Detected Severity:
12	RWCS	0b	0 =	ERR_NONFATAL
			1 =	ERR_FATAL

			PCI-X PERR# Detected Severity:
11	RWCS	0b	0 =	ERR_NONFATAL
			1 =	ERR_FATAL

			PCI Delayed Transaction Timer Expiry Severity:
10	RWCS	0b	0 =	ERR_NONFATAL
			1 =	ERR_FATAL

			PCI-X Uncorrectable Address Parity Error Detected Severity:
9	RWCS	0b	0 = ERR_NONFATAL
			1 =	ERR_FATAL

			PCI-X Uncorrectable Attribute Parity Error Detected Severity:
8	RWCS	0b	0 = ERR_NONFATAL
			1 =	ERR_FATAL

			PCI-X Uncorrectable Data Parity Error Detected Severity:
7	RWCS	0b	0 = ERR_NONFATAL
			1 =	ERR_FATAL

			Split Completion Message Data Error Severity:
6	RWS	1b	0 =	ERR_NONFATAL
			1 =	ERR_FATAL

			Unexpected Split Completion Error Severity:
5	RWS	0b	0 =	ERR_NONFATAL
			1 =	ERR_FATAL

4	RsvdP	0b	Preserved

			PCI-X Detected Master Abort Severity:
3	RWCS	0b	0 = ERR_NONFATAL
			1 =	ERR_FATAL

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

115

Image 115

Intel 41210 manual Internal Bridge Data Error Severity, PCI-X SERR# Detected Severity, PCI-X PERR# Detected Severity

Contents

Developer’s Manual Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision History PCI-X Interface Features PCI Express* Interface FeaturesIntroduction1 SMBus Interface Power ManagementJtag On-Die Termination ODT Signal Description AGNT#50 BGNT#50 ODT SignalsAACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ADEVSEL# BDEVSEL# AFRAME# BFRAME# Total PCI Express* Interface PinsPCI Express* Interface PERCOMP10 AIRDY# PCI Interface Pins Sheet 1PCI Bus Interface Two Instances ADEVSEL# PCI Interface Pins Sheet 2 PCI Clock and Reset Pins PCI Interface Pins 64-Bit ExtensionsPCI Bus Interface 64-Bit Extension Two Interfaces AINTC# AINTD# Interrupt Interface PinsInterrupt Interface Two Interfaces AINTA# AINTB# Reset Strap Pins Reset StrapsCfgretry SMBus Interface Pins Miscellaneous Pins Miscellaneous Pins Number Description Voltage Pins This page Intentionally Left Blank PCI-X Initialization Pattern PCI Mode Pin/Strap EncodingPCI-X Interface Initialization Transaction Encoding1 PCI ModeTransactions Supported PCI Transactions Supported Read Transactions PCI-X ModePCI-X Transactions Supported Delayed Configuration Transactions End Point Source Lock CyclesPCI Transaction Termination Decoding PCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Wait States PCI-X Protocol SpecificsAttributes 2 4 GB and 4 K Page Crossover Split Completion Abort Registers ArbitrationSplit Transactions Fields BridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration Scheme PCI Bus Power Management Power ManagementHardware-Controlled Active State Power Management Software-Driven PCI-PM 1.1-Compatible Power Management Power-Management Event Signaling Pmetoack This page Intentionally Left Blank Addressing5 Addressable Space AccessPCI-to-PCI Bridge a Configuration Space PCI-to-PCI Bridge B Configuration Space Secondary PCI Devices Configuration-Space AccessPCI Express* Configuration Access Device Number Signal Used for Public/Private Addressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X Interface SMBus Configuration Access I/O Space Access Mechanism O Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O Window Prefetchable Memory Window VGA AddressingOpaque Memory Window § § Row Pass Column Transaction OrderingUpstream Transaction Ordering Upstream Transaction Ordering Relaxed Ordering/No-Snoop Support Downstream Transaction OrderingDownstream Transaction Ordering Legacy Interrupt Sharing Interrupt SupportINTx Routing Table Secondary Bus Interrupt Routing for Devices behind a BridgeInterrupt Binding for Devices behind a Bridge Device Number on SMBus Address Assignments System Management Bus InterfaceBit Value SMBus command SMBus CommandsSMBus Command Encoding Internal Command Initialization Sequence ConfigurationSMBus Status Byte Encoding Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Clock Domains Clock and ResetDevice Reset Clocking RSTIN# Reset Mechanism PERST# Reset MechanismPCI Express* Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Express* Errors Error HandlingPCI Errors PCI-X Termination PCI Express* Completion Error TypesTermination of Completion Required Transactions Completion-Status Translation for Immediate Terminations Index PCI-X Split Termination Message PCI ExpressSuccessful 00h PCI Express* Completion Status PCI Completion Split Termination on PCI Express* Interface Bit Attribute Definitions Register Nomenclature and Access AttributesPERST# reset Register Description Configuration Registers B3174-02 PCI/PCI-X Compatible Configuration regionCapptr 0xFFF 0x300 0x100 0x40 0x00 Legacy Configuration Space Register PCI Express* Extended Configuration SpaceByte Offset Offset 00h ID-Identifiers Offset 04h PCICMD-Command RegisterOffset 04h PCICMD-Command Register Sheet 1 Reset Description Type Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Offset 06h PSTS-Primary Device Status Sheet 1 Bits Offset 08h REVID-Revision IDOffset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision ID Offset 0Eh HEADTYP-Header Type Offset 0Dh PMLT-Primary Master Latency TimerOffset 09h CC-Class Code Offset 0Ch CLS-Cache-Line Size Offset 18h BNUM-Bus Numbers Offset 1Bh SMLT-Secondary Master Latency TimerOffset 1Bh SMLT-Secondary Master Latency Timer Offset 18h BNUM-Bus Numbers Support for 16-bit I/O addressing only Offset 1Ch IOBL-I/O Base and LimitOffset 1Ch IOBL-I/O Base and Limit FFFh Offset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status Must be less than this value Offset 20h MBL-Memory Base and LimitOffset 20h MBL-Memory Base and Limit 3120 000h Offset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 24h PMBL-Prefetchable Memory Base and Limit Offset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 3Ch INTR-Interrupt Information Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 34h CAPP-Capabilities List Pointer Offset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 2 Bit Maximum Number of Upstream Delayed Transactions Offset 40h BCNF-Bridge Configuration RegisterOffset 40h BCNF-Bridge Configuration Register Peer Memory Read Enable Pmre Offset 45h EXPNXTP-Next Item Pointer Offset 42h MTT-Multi-Transaction TimerOffset 43h PCLKC-PCI Clock Control Offset 44h EXPCAPID-PCI Express* Capability Identifier Offset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxReadRequestSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxPayloadSize Offset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 4Eh EXPDSTS-PCI Express* Device Status Register L0s Exit Latency Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register Offset 54h EXPLCTL-PCI Express* Link Control Register Offset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 5Eh MSIMC-PCI Express* MSI Message Control Offset 60h MSIMA-PCI Express* MSI Message Address Offset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item Pointer Offset 72h PMBSE-Power Management Bridge Support Extensions Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 73h PMDATA-Power Management Data Field Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities Identifier Offset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge Status Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization Register When the configuration unit signals a completer abort Power Budgeting Capability as the next capabilityAdvanced Error Reporting Extended Capability Version Number ID, indicating Advanced Error Reporting Capability Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Training Error Severity Not supported Unsupported Request Error Status SeverityFlow Control Protocol Error Status Severity Data Link Protocol Error Severity Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log1270 Sheet 1 Logs the header Sheet 2 PCI-X Uncorrectable Attribute Parity Error Detected Mask Internal Bridge Data Error MaskPCI Delayed Transaction Timer Expiry Mask PCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specification PCI-X Uncorrectable Data Parity Error Detected Severity Internal Bridge Data Error SeverityPCI Delayed Transaction Timer Expiry Severity PCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Detected Split Completion Master Abort Severity Rwcs = Errnonfatal = ErrfatalRegister is cleared by the software writing a 1 to the bit Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log SMBUS5 SMBUS3 SMBUS2 SMBUS1 Offset 170h SSR-Strap Status RegisterOffset 170h SSR-Strap Status Register Reserved Read only Offset 178h PREFCTRL-Prefetch Control Register Offset 178h PREFCTRL-Prefetch Control Register6360 RsvdP Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select Register