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Intel 41210 12.2.61 Offset 134h: PCIXERRUNC_SEVUncorrectable PCI-X Error Severity Register

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Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 115

Register Description

12.2.61 Offset 134h: PCIXERRUNC_SEV—UncorrectablePCI-X Error Severity Register

This register controls the severity of the reporting of PCI-X uncorrectable errors. There is one

mask bit per error. When a bit is set to 1, the corresponding error, when enabled, generates an

ERR_FATAL message on PCI Express*. When a bit is cleared to 0, the corresponding error,

when enabled, causes a ERR_NONFATAL on PCI Express*.

Table 95. Offset 130h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register

(Sheet 1 of 2)

Bits Type Reset Description

15:14 RsvdP 00b Preserved

13 RWCS 0b

Internal Bridge Data Error Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

12 RWCS 0b

PCI-X SERR# Detected Severit y:

0 = ERR_NONFATAL

1 = ERR_FATAL

11 RWCS 0b

PCI-X PERR# Detected Severit y:

0 = ERR_NONFATAL

1 = ERR_FATAL

10 RWCS 0b

PCI Delayed Transaction Timer Expiry Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

9RWCS 0b

PCI-X Uncorrectable Address Parity Error Detected Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

8RWCS 0b

PCI-X Uncorrectable Attribute Parity Error Detected Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

7RWCS 0b

PCI-X Uncorrectable Data Parity Error Detected Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

6RWS 1b

Split Completion Message Data Error Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

5RWS 0b

Unexpected Split Completion Error Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

4 RsvdP 0b Preserved

3RWCS 0b

PCI-X Detected Master Abort Severity:

0 = ERR_NONFATAL

1 = ERR_FATAL

Contents

Main 2Intel 41210 Serial to Parallel PCI Bridge Developers Manual Contents Page Page Figures Tables Page Page Revision History Introduction 1 1.1 PCI Express* Interface Features 1.2 PCI-X Interface Features 1.3 Power Management 1.4 SMBus Interface 1.5 JTAG Signal Description 2 2.1 On-Die Termination (ODT) 14 Intel 41210 Serial to Parallel PCI Bridge Developers Manual Table 1. ODT Signals Intel 41210 Serial to Parallel PCI Bridge Developers Manual 15 2.2 PCI Express* Interface Table 2. PCI Express* Interface Pins 16 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 2.3 PCI Bus Interface (Two Instances) Intel 41210 Serial to Parallel PCI Bridge Developers Manual 17 Table 3. PCI Interface Pins (Sheet 2 of 2) 18 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces) Tota l 2.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces) Table 4. PCI Interface Pins: 64-Bit Extensions Tota l 2.6 Interrupt Interface (Two Interfaces) 20 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 2.7 Reset Straps Tot al Intel 41210 Serial to Parallel PCI Bridge Developers Manual 21 2.8 SMBus Interface Tota l Table 8. SMBus Interface Pins 22 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 2.9 Miscellaneous Pins Tot al Table 9. Miscellaneous Pins Intel 41210 Serial to Parallel PCI Bridge Developers Manual 23 2.10 Voltage Pins Tota l Table 10. Miscellaneous Pins Page PCI-X Interface 3 3.1 Initialization 3.2 Transactions Supported 3.2.1 PCI Mode 3.2.2 PCI-X Mode 3.2.3 Read Transactions 3.2.3.1 Prefetchable 3.2.4 Configuration Transactions 3.2.5 LOCK Cycles 3.2.6 Decoding 3.2.7 Transaction Termination 3.2.7.1 PCI Mode Transaction Termination Page 3.2.7.2 PCI-X Mode Transaction Termination Page 3.3 PCI-X Protocol Specifics 3.3.1 Attributes 3.3.2 4 GB and 4 K Page Crossover 3.3.3 Wait States 3.3.4 Split Transactions 3.4 Arbitration Page Power Management 4 4.1 Hardware-Controlled Active State Power Management 4.2 Software-Driven PCI-PM 1.1Compatible Power Management 4.3 PCI Bus Power Management 4.4 Intel 41210 Serial to Parallel PCI Bridge Device Power Management 4.5 Power-Management Event Signaling Page Page Addressing 5 5.1 Addressable Spaces within the Intel 41210 Serial to Parallel PCI Bridge 5.2 Secondary PCI Devices 5.3 Configuration-Space Access 5.3.1 PCI Express* Configuration Access Page 5.3.2 Type 0 Configuration Access from PCI-X Interface 5.3.3 SMBus Configuration Access 5.4 I/O Space Access Mechanism Page 5.5 Memory Space Access Mechanism 5.5.1 Memory-Mapped I/O Window 5.5.2 Prefetchable Memory Window 5.5.3 Opaque Memory Window 5.6 VGA Addressing Page Transaction Ordering 6 6.1 Upstream Transaction Ordering 6.2 Downstream Transaction Ordering 6.3 Relaxed Ordering/No-Snoop Support Interrupt Support 7 7.1 Legacy Interrupt Sharing 54 Intel 41210 Serial to Parallel PCI Bridge Developers Manual Interrupt Support 7.2 Interrupt Routing for Devices behind a Bridge Table 24. Interrupt Binding for Devices behind a Bridge System Management Bus Interface 8 8.1 SMBus Commands Block Write Word Write Byte Write Block Read Word Read Byte Read 8.2 Initialization Sequence 8.2.1 Configuration 58 Intel 41210 Serial to Parallel PCI Bridge Developers Manual Figure 7. DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) Intel 41210 Serial to Parallel PCI Bridge Developers Manual 59 Figure 9. DWord Configuration Read Protocol (SMBus Word Write/Word R ead, PEC Disab led) 8.2.2 Configuration Writes 8.3 Error Handling 8.4 SMBus Interface Reset Local Initialization 9 Page Clock and Reset 10 10.1 Clocking 10.2 Device Reset 10.2.1 PERST# Reset Mechanism 10.2.2 RSTIN# Reset Mechanism 10.2.3 PCI Express* Reset Mechanism 10.2.4 Software PCI Reset (SBRSecondary Bus Reset) Page Error Handling 11 11.1 PCI Express* Errors 11.2 PCI Errors 11.2 .1 Erro r Typ es 11.2.2 Termination of Completion Required Transactions 11.2.2.1 Immediate Termination on the PCI-X Interface 11.2.2.2 Split Termination on PCI-X Interface 72 Intel 41210 Serial to Parallel PCI Bridge Developers Manual Error Handling 11.2.2.3 Split Termination on PCI Express* Interface Table 31. Completion-Status Translation for PCI Express* Split-Completion Terminations Intel 41210 Serial to Parallel PCI Bridge Developers Manual 73 Register Description 12 This chapter describes the registers of the Intel 41210 Serial to Parallel PCI Bridge. 12.1 Register Nomenclature and Access Attributes Tabl e 32 describes the nomenclature used for describing bit attributes throughout this chapter. Table 32. Bit Attribute Definitions 12.2 Configuration Registers Intel 41210 Serial to Parallel PCI Bridge Developers Manual 75 Figure 12. Intel 41210 Serial to Parallel PCI Bridge Capabilities Extended Configuration Space 76 Intel 41210 Serial to Parallel PCI Bridge Developers Manual Table 33. Legacy Configuration Space Intel 41210 Serial to Parallel PCI Bridge Developers Manual 77 Table 34. PCI Express* Extended Configuration Space 78 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.1 Offset 00h: IDIdentifiers Contains the vendor and device identifiers for software. 12.2.2 Offset 04h: PCICMDCommand Register Table 35. Offset 00h: IDIdentifiers Table 36. Offset 04h: PCICMDCommand Register (Sheet 1 of 2) 12.2.3 Offset 06h: PSTSPrimary Device Status Table 36. Offset 04h: PCICMDCommand Register (Sheet 2 of 2) Table 37. Offset 06h: PSTSPrimary Device Status (Sheet 1 of 2) 80 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.4 Offset 08h: REVIDRevision ID This register is the Revision ID Register. Table 37. Offset 06h: PSTSPrimary Device Status (Sheet 2 of 2) Table 38. Offset 08h: REVIDRevision ID 12.2.5 Offset 09h: CCClass Code 12.2.6 Offset 0Ch: CLSCache-Line Size 12.2.7 Offset 0Dh: PMLTPrimary Master Latency Timer 12.2.8 Offset 0Eh: HEADTYPHeader Type 12.2.9 Offset 18h: BNUMBus Numbers 12.2.10 Offset 1Bh: SMLTSecondary Master Latency Timer 12.2.11 Offset 1Ch: IOBLI/O Base and Limit 84 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.12 O ffset 1Eh: SSTSSecondary Status 12.2.13 Offset 20h: MBLMemory Base and Limit 12.2.14 Offset 24h: PMBLPrefetchable Memory Base and Limit 12.2.15 Offset 28h: PMBU32Prefetchable Memory Base Upper 32 Bits 12.2.16 Offset 2Ch: PMLU32Prefetchable Memory Limit Upper 32 Bits 12.2.17 Offset 30h: IOBLU16I/O Base and Limit Upper 16 Bits 12.2.18 Offset 34h: CAPPCapabilities List Pointer 12.2.19 Offset 3Ch: INTRInterrupt Information 88 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.20 Offset 3Eh: BCTRLBridge Control Intel 41210 Serial to Parallel PCI Bridge Developers Manual 89 Table 54. Offset 3Eh: BCTRLBridge Control (Sheet 2 of 2) 90 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.21 Offset 40h: BCNFBridge Configuration Register 12.2.22 Offset 42h: MTTMulti-Transaction Timer 12.2.23 Offset 43h: PCLKCPCI Clock Control 12.2.24 Offset 44h: EXP_CAPIDPCI Express* Capability Identifier 12.2.25 Offset 45h: EXP_NXTPNext Item Pointer 92 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.26 Offset 46h: EXP_CAPPCI Express* Capability This register stores information on the PCI Express* link capabilities. 12.2.27 Offset 48h: EXP_DCAPPCI Express* Device Capabilities Table 60. Offset 46h: EXP_CAPPCI Express* Capability Table 61. Offset 48h: EXP_DCAPPCI Express* Device Capabilities Register 12.2.28 Offset 4Ch: EXP_DCTLPCI Express* Device Control 94 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.29 Offset 4Eh: EXP_DSTSPCI Express* Device Status This register stores information on the PCI Express* device status. 12.2.30 Offset 50h: EXP_LCAPPCI Express* Link Capabilities Table 62. Offset 4Ch: EXP_DCTLPCI Expres s* Device Control Register (Sheet 2 of 2) Table 63. Offset 4Eh: EXP_DSTSPCI Express* Dev ice Status Register 12.2.31 Offset 54h: EXP_LCTLPCI Express* Link Control Register Intel 41210 Serial to Parallel PCI Bridge Developers Manual 95 Table 65. Offset 54h: EXP_LCTLPCI Expr ess* Link Control Register Table 64. Offset 50h: EXP_LCAPPCI Express* Link Capabilities Register (Sheet 2 of 2) 96 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.32 Offset 56h: EXP_LSTSPCI Express* Link Status Register 12.2.33 Offset 5Ch: MSI_CAPIDPCI Express* MSI Capability Identifier 12.2.34 Offset 5Dh: MSI_NXTPPCI Express* Next Item Pointer Note: MSI generation is used for internal debugging purposes and does not occur in normal operation. Table 66. Offset 56h: EXP_LSTSPCI Express* Link Status Register 12.2.35 Offset 5Eh: MSI_MCPCI Express* MSI Message Control 12.2.36 Offset 60h: MSI_MAPCI Express* MSI Message Address Table 69. Offset 5Eh: MSI_MCPCI Express* M SI Message Control Table 70. Offset 60h: MSI_MAPCI Express* M SI Message Address Table 71. Offset 68h: MSI_MDPCI Express* M SI Message Data 98 Intel 41210 Serial to Parallel PCI Bridge Developers Manual Table 73. Offset 6Dh: PM_NXTPPower Management Next Item Pointer Table 74. Offset 6Eh: PM_PMCPower Management Capabilities Intel 41210 Serial to Parallel PCI Bridge Developers Manual 99 12.2.41 Offset 70h: PM_PMCSRPower Management Control/Status Register 12.2.42 Offset 72h: PM_BSEPower Management Bridge Support Extensions 12.2.43 Offset 73h: PM_DATAPower Management Data Field Table 75. Offset 70h: PM_PMCSRPower Mana gement Control/Status Register Table 76. Offset 72h: PM_BSEPower Management Bridge Support Extensions 12.2.44 Offset D8h: PX_CAPIDPCI-X Capabilities Identifier 12.2.45 O ffset D9h: PX_NXTPPCI-X Next Item Pointer Intel 41210 Serial to Parallel PCI Bridge Developers Manual 101 12.2.46 Offset DAh: PX_SSTSPCI-X Secondary Status 102 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.47 O ffset DCh: PX_BSTSPCI-X Bridge Status This register identifies PCI-X status register for the bridge primary side. 12.2.48 O ffset E0h: PX_USTCPCI-X Upstream Split Transaction Control Table 81. Offset DCh: PX_BSTSPCI-X Brid ge Status Table 82. Offset E0h: PX_USTCPCI-X Upstream Split Transaction Control 12.2.49 Offset E4h: PX_DSTCPCI-X Downstream Split Transaction Control 104 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.50 Offset FCh: BINITBridge Initialization Register Table 84. Offset FCh: BINITBridge Initialization Register Intel 41210 Serial to Parallel PCI Bridge Developers Manual 105 12.2.51 Offset 100h: EXPAERR_CAPIDPCI Express* Advanced Error Capability Identifier This register stores the PCI Express* extended capability ID value. 12.2.52 Offset 104h: ERRUNC_STSPCI Express* Uncorrectable Error Status Register Table 85. Offset 100h: EXPAERR_CAPIDPCI Express* Advanced Error Capability Identifier Table 86. Offset 104h: ERRUNC_STSPCI Expr ess* Uncorrectable Error Status Register 12.2.53 O ffset 108h: ERRUNC_MSKPCI Express* Uncorrectable Error Mask Intel 41210 Serial to Parallel PCI Bridge Developers Manual 107 12.2.54 Offset 10Ch: ERRUNC_SEVPCI Express* Uncorrectable Error Severity 12.2.55 O ffset 110h: ERRCOR_STSPCI Express* Correctable Error Status Intel 41210 Serial to Parallel PCI Bridge Developers Manual 109 12.2.56 Offset 114h: ERRCOR_MSKPCI Express* Correctable Error Mask 12.2.57 Offset 118h: ADVERR_CTLAdvanced Error Control and Capability Register Table 90. Offset 114h: ERRCOR_MSKPCI Express* Correctable Error Mask Table 91. Offset 118h: ADVERR_CTLAdvanced Error Control and Capability Register Page Intel 41210 Serial to Parallel PCI Bridge Developers Manual 111 12.2.59 Offset 12Ch: PCIXERRUNC_STSUncorrectable PCI-X Status Register Table 93. Offset 12Ch: PCIXERRUNC_STSUncorrectable PCI-X Status Register Page Intel 41210 Serial to Parallel PCI Bridge Developers Manual 113 12.2.60 Offset 130h: PCIXERRUNC_MSKUncorrectable PCI-X Error Mask Register Page Intel 41210 Serial to Parallel PCI Bridge Developers Manual 115 12.2.61 Offset 134h: PCIXERRUNC_SEVUncorrectable PCI-X Error Severity Register 12.2.62 Offset 138h: PCIXERRUNC_PTRUncorrectable PCI-X Error Pointer Intel 41210 Serial to Parallel PCI Bridge Developers Manual 117 12.2.63 Offset 13C14Bh: PCIXHDR_LOGUncorrectable PCI-X Error Transaction Header Log 12.2.64 Offset 16Ah: ARB_CNTRLInternal Arbiter Control Table 97. Offset 13C14Bh: PCIXHDR_LOGUncorrectable PCI-X Header Log Table 98. Offset 16Ah: ARB_CNTRLInternal Arbiter Control Register 118 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.65 O ffset 170h: SSRStrap Status Register Intel 41210 Serial to Parallel PCI Bridge Developers Manual 119 12.2.66 Offset 178h: PREFCTRLPrefetch Control Register 120 Intel 41210 Serial to Parallel PCI Bridge Developers Manual 12.2.67 Offset 300h: PWRBGT_CAPIDPower Budgeting Enhanced Capability Header This register defines the capability identifier. 12.2.68 Offset 304h: PWRBGT_DSELPower Budgeting Data Select Register 12.2.69 Offset 308h: PWRBGT_DATAPower Budgeting Data Table 101. Offset 300h: PWRBGT_HDRPower Budgeting Enhanced Capability Header