Intel 41210 manual Hardware-Controlled Active State Power Management, PCI Bus Power Management

	Power Management
Power Management	4

4.1Hardware-Controlled Active State Power Management

PCI Express* defines a hardware-initiated power management of the PCI Express* Link called active state power management. Under hardware control, the link can be put into a low-power L0s link state or an even lower-power L1 link state. The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge or the 41210) supports only the PCI Express* active state power management link state L0s. The 41210 does not support optional active state power management link state L1. Active state power management is entirely dependent on traffic and is not initiated by software. The software, however, can enable and disable the active state management by means of the capability structure.

Note: Due to the unreliable behavior described in the Intel 41210 Serial to Parallel PCI Bridge Specification Update, Errata #19, L0s active state power management is not supported.

Refer to the PCI Express* Specification, Revision 1.0a for more details on the active state power management.

Note: Link state L1 is not supported for hardware-driven active state power management. However, link state L1 is supported for software-driven power management.

4.2Software-Driven PCI-PM 1.1–Compatible Power Management

The 41210 supports PCI Express* link states L0, L1, and L3, as required to implement PCI-PM 1.1–compatible device states (D0, D3hot, D3cold). When both bridge segments in the 41210 are programmed to the D3hot state, the PCI Express* link enters the link state L1. When the PCI Express* link is in L1 because of software-driven power management, the only message that can cause the link to come out of L1 is a PME message.

Refer to the PCI Express* Specification, Revision 1.0a for details of the protocol involved in transitioning the link to the L1 state.

The 41210 also supports the PM_TURN_OFF/PM_TO_ACK protocol to support D3cold/L3 device/link states.

4.3PCI Bus Power Management

The 41210 supports bus states B0 and B3 corresponding to the bridge device states D0 and D3cold. The 41210 does not support stopping the PCI bus clocks when in D3hot state and hence does not support the bus state B2.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 37