Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 17
Signal Description
A_PERR#
B_PERR# I/O
Parity Error: PERR# is driven by an external PCI device when it receives data that has a parity error.
PERR# is driven by the 41210 in the following cases:
• when the 41210, as an initiator, detects a parity error during a read transaction
• when the 41210, as a target, detects a parity error during a write transaction
No external pull-up resistors are required on the system board for these signals.
A_SERR#
B_SERR# ISystem Error: The 41210 samples SERR# as an input and conditionally forwards it to the PCI
Express*.
No external pull-up resistors are required on the system board for these signals.
A_REQ#[5:0]
B_REQ#[5:0] IPCI Requests: REQ# receives request inputs into the internal arbiter.
No external pull-up resistors are required on the system board for these signals.
A_GNT#[5:0]
B_GNT#[5:0] OPCI Grants: GNT# is the bus grant output corresponding to request input bits[5:0] from the internal
arbiter. GNT# indicates that an initiator can start a transaction on the PCI bus.
No external pull-up resistors are required on the system board for these signals.
A_M66EN
B_M66EN I/OD
66 MHz Enable: M66EN is an input signal from the PCI bus that indicates the speed of the PCI bus.
When it is high, the bus speed is 66MHz. When it is low, the bus speed is 33 MHz. This signal is
used to generate an appropriate clock (33 or 66 MHz) on the PCI bus.
To tie high: Use an approximately 8.2KΩ resistor to pull to VCC33.
To tie low: Pull down to ground.
A_PCIXCAP
B_PCIXCAP IPCI-X Capable: PCIXCAP indicates whether all devices on the PCI bus are PCI-X devices, so that
the 41210 can switch into PCI-X mode. Use an approximately 8.2 KΩ resistor to pull to VCC33.
A_LOCK#
B_LOCK# O
PCI Lock: LOCK# indicates an exclusive bus operation and may require multiple transactions to
complete. This signal is an output from the bridge when it is initiating exclusive transactions on PCI.
LOCK# is ignored when PCI masters are granted the bus. Locked transaction do not propagate
upstream.
No external pull-up resistors are required on the system board for these signals.
Tota l 118
Table 3. PCI Interface Pins (Sheet 2 of 2)
Signal I/O Description