38 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
Power Management
4.4 Intel® 41210 Serial to Parallel PCI Bridge Device Power Management
Each bridge segment supports PCI-PM1.1 device power management states D0, D3hot, and
D3cold. Each function, when programmed to the D3hot state, behaves as follows:
•The function responds to configuration cycles from PCI Express*.
•The function initiates and accepts PCI Express* completion transactions.
•The function does not respond to memory cycles on PCI Express*.
•The function does not respond to I/O cycles on PCI Express*.
•The function does not initiate PCI Express* request transactions.
•The function does not reset its registers, when programmed to D0 from D3hot.
•The 41210 does not assert PCIRST# when in the D3hot state.
4.5 Power-Management Event Signaling
The 41210 supports conveying PCI power-management events (PME#) over PCI Express* by
means of an in-band mechanism. Power-management events are generated on behalf of PCI
devices that require a change in their power state. The 41210 does not support any method to
“wake” the PCI Express* hierarchy before it signals a PME message (in other words, the 41210
supports neither the WAKE# side band signal nor the in-band tone-generation mechanism).
Waking is needed when the upstream component is in a non-communicative state with clock and/or
power removed. The expectation for this component is that both ends of the link are fully powered
and clocked (in other words, the link is fully communicative) when signaling the PCI power-
management events.
The 41210 supports a PME# event pin for conveying power-management events that occur on the
secondary PCI bus segments of the 41210. The PME output from all the PCI devices on the
segment are wire-ORed to obtain a composite PME signal which is routed to th e 41210 . The 4 1210
converts the level-sensitive PME# signal into a PCI Express* message. This message carries the
bus number of the PCI bus that caused the PME# assertion. The power-manager software needs the
bus-number information when invoked.
Note: Since the bus number of the PCI bus must be passed in the PME_MSG, this scheme functions
correctly only for waking from the PCI buses directly below the 41210.
The exact mechanism for generating the PME_MSG packet in the 41210 involves sending a
message over PCI Express* whenever the PME input pin is asserted. Note that this packet must
carry the bus number of the PCI bus generating the PME#. This means that the 41210 must
construct the requestor ID of the PME_MSG packet with the secondary bus-number register in the
corresponding PCI-to-PCI Bridge header space. There is a chance that PME messages could be
lost. Thus the 41210 implements a counter to periodically sample the PME# pin and generate a
message. Refer to the PCI Express* specifications for more details. This polling mechanism
creates spurious interrupts to the power-manager software, and the power manager must be able to
handle this.