Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 47
Addressing
5.5 Memory Space Access Mechanism
The 41210 supports 64 bits of memory addressing on both interfaces.
Two memory windows can be setup for forwarding memory transactions from PCI Express*-to-
PCI. These windows are defined as part of the standard PCI-to-PCI Bridge configuration space.
Inverse decoding is used for forwarding transactions from PCI-to-PCI Express*. Refer to
Section 5.6, “VGA Addressing” on page 49 to see how memory cycles in the VGA range are
handled. The registers and register bits listed below control the setup and operation of these
memory windows:
•Memory-mapped I/O base and limit (MBL) registers
•Prefetchable memory base and limit (PMBL) registers
•Prefetchable memory base and limit upper 32bits (PMBLU32) register
•Memory enable (MSE) bit in the command register
•Master enable bit (BME) in the command register
To enable downstream memory transactions, the memory space enable bit in the command register
must be set (bit[1] of offset 04h–05h). To enable ups tream memo ry t ran sact ion s, the mast er enabl e
bit in the command register must be set (bit[2] of offset 04h–05h). The 41210 does not prefetch
data from downstream PCI devices. Upstream prefetching is controllable by settings in the “Offset
178h: PREFCTRL—Prefetch Control Register” on page119.