94 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

Register Description
12.2.29 Offset 4Eh: EXP_DSTS—PCI Express* Device Status
Register

This register stores information on the PCI Express* device status.

12.2.30 Offset 50h: EXP_LCAP—PCI Express* Link Capabilities
Register
2RW 0b
Report Fatal Errors: When this bit is set, generation of the ERR_FATAL message is
enabled.
1RW 0b
Report NonFatal Errors: When this bit is set, generation of the ERR_NONFATAL message
is enabled.
0RW 0b
Report Correctable Errors: When this bit is set, generation of the ERR_CORR message is
enabled.

Table 62. Offset 4Ch: EXP_DCTL—PCI Expres s* Device Control Register (Sheet 2 of 2)

Bits Type Default Description

Table 63. Offset 4Eh: EXP_DSTS—PCI Express* Dev ice Status Register

Bits Type Default Description
15:6 RsvdZ 000h Reserved Zero: Software must always write a 0 to these bits.
5RO 0b
Transactions Pending: This bit is set when any non-posted request has been issued but
has not been completed. The bit is cleared only when all completions for all outstanding
non-posted requests are received. Note that this is a dynamic bit; in other words, this bit
goes on and off based on current traffic.
4RO 0b
Auxiliary Power Detected: Auxiliary Power is not supported.
3RWC 0b
Unsupported Request Detected: This bit is set when any unsupported request from PCI
Express* is received. Unsupported requests include all requests that are not claimed by any
function in the Intel® 41210 Serial to Parallel PCI Bridge, but do not include requests
forwarded to the PCI interface with completions returned with an “unsupported request”
status.
2RWC 0b
Detected Fatal Error: This bit is set when a fatal error is detected (regardless of whether
an error message is generated) on either interface or internally. The bit remains set until the
software writes a 1 to clear it.
1RWC 0b
Detected Non-Fatal Error: This bit is set when a non-fatal error is detected (regardless of
whether the mask bit is set in the advanced error capability) on either interface or internally.
The bit remains set until the software writes a 1 to clear it.
0RWC 0b
Detected Correctable Error: This bit is set when a correctable error is detected
(regardless of whether the mask bit is set in the advanced error capability) on either
interface or internally. The bit remains set until the software writes a 1 to clear it.

Table 64. Offset 50h: EXP_LCAP—PCI Express* Link Capabilities Register (Sheet 1 of 2 )

Bits Type Default Description
31:24 RO 00h Port Number: Not applicable
23:18 RsvdP 00h Preserved
17:15 RO 111b L1 Exit Latency: L1 transition is not supported.