Intel 41210 1.3 Power Management, 1.4 SMBus Interface, 1.5 JTAG

12 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
Introduction
•Up to two downstream delayed (memory read, I/O read/write and configuration read/write)
transactions
•Tunable inbound read prefetch algorithm for PCI MRM/MRL commands
•Device hiding support for secondary PCI devices
•Secondary bus private memory support via opaque memory region
•Local initialization via SMBus
•Secondary side initialization via Type 0 configuration cycles
•Full peer-to-peer read/write capability between the two secondary PCI segments
1.3 Power Management
•Support for PCI PM 1.1-compatible D0, D3hot and D3cold device power states
•Support for PME# event propagation on behalf of PCI devices
1.4 SMBus Interface
•Compatible with System Management Bus Specification, Revision 2.0
•Slave-mode operation only
•Full read/write access to all configuration registers
1.5 JTAG
•IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a