Intel 41210 Secondary PCI Devices, Configuration-Space Access, PCI Express* Configuration Access

Addressing

5.2Secondary PCI Devices

Devices on the secondary PCI bus can be configured as private devices and hidden from BIOS and host software. Devices are hidden by inhibiting the assertion of the IDSEL input of the device during configuration cycles. This feature is configured through the BINIT register. Public and private devices are supported according to Table 20.

Table 20. Secondary PCI Device Addressing

Device Number	Signal Used for	Public/Private	Notes
	IDSEL Input
0	AD16	Reserved	Dedicated for bridge
1	AD17
2	AD18
3	AD19		Based on the device-hiding enable bit
4	AD20	Public or Private	(bit[2] of the BINIT register)
			Available for secondary PCI devices
5	AD21
6	AD22
7	AD23
8	AD24		Used to address extended configuration
9	AD25	Reserved	space of bridge
			Based on the upstream-configuration
10 (0xA)	AD26
			enable bit (bit[1] of the BINIT register)
11 (0xB)	AD27
12 (0xC)	AD28
13 (0xD)	AD29	Public	Available for secondary PCI devices
14 (0xE)	AD30
15 (0xF)	AD31

5.3Configuration-Space Access

The 41210 supports configuration-space accesses from PCI Express* using both the legacy PCI-to- PCI Bridge Specification, Revision 2.3 access mechanism and the enhanced PCI Express* configuration-space access mechanism. For local initialization, the 41210 also supports configuration-pace accesses from the SMBus port and secondary PCI bus.

5.3.1PCI Express* Configuration Access

The PCI-to-PCI Bridge Specification, Revision 1.1 defines the configuration-space region of a PCI function to be up to 256 B. PCI Express* extends the PCI configuration space from 256 B to 4 K. The region up to 256 B can be accessed using the mechanism for configuration accesses defined in the PCI-to-PCI Bridge Specification, Revision 1.1. The region above 256 B is accessible only by means of the enhanced configuration access mechanism defined in PCI Express*. This mechanism utilizes a flat memory-mapped address region to access the configuration space. The core-logic chipset converts the legacy PCI-to-PCI Bridge Specification, Revision 1.1 or the enhanced PCI Express* configuration-space accesses into PCI Express* configuration cycles.

42 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual