48 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
Addressing
5.5.1 Memory-Mapped I/O Window
Software uses the memory-mapped I/O window to map all non-prefetchable (in ot her words , reads
that have side effects, such as reads to FIFOs, or “read-to-clear” status registers) memory space
into PCI memory space.
The memory-mapped I/O base address register and memory-mapped I/O limit address register
define an address range that the bridge uses to determine when to forward memory commands. The
41210 forwards a memory transaction from PCI Express* to PCI when the address falls within the
range. The 41210 forwards it from PCI to PCI Express* (or the peer PCI segment) when the
address is outside the range and does not fall into the prefetchable memory range. This memory
range supports 32-bit addressing only (addresses 4GB). It has a granularity and alignment of
1MB.
This range is defined by a 16-bit base address register at offset 20h in the configuration space and a
16-bit limit address register at offset 22h. The most significant 12bits of each of these registers
correspond to bits[31:20] of the memory address. The least significant fourbits are hard-wired to 0.
The least significant 20 bits of the base address are assumed to be all 0s, which results in a natural
alignment to a 1 MB boundary. The least significant 20bits of the limit address are assumed to be
all 1s, which results in an alignment to the top of a 1 MB block.
Note: Setting the base to a value greater than that of the limit turns off the memory range.
Figure 5. Memory Forwarding
B3186-01
Primary Secondary
Prefetchable Limit
Prefetchable Base
Prefetchable Memory
263
264
4 GB
0 K
Non-Prefetchable Limit
Non-Prefetchable Base
Private A-Segment Memory
(optional)
Memory Mapped I/O