Intel 41210 manual Configuration Transactions, Delayed

PCI-X Interface

3.2.3.2Delayed

All memory read transactions are delayed read transactions. When the 41210 accepts a delayed read request, it samples the address, command, and address parity. This information is entered into the delayed transaction queue. When the 41210 is in PCI-X mode, transactions follow the split transaction model of PCI-X. Read data returned from PCI Express* for an active delayed transaction entry is forwarded to the PCI-X master as a split completion.

3.2.3.3Inbound Read Request Algorithm

In PCI mode:

•Each read stream always gets exactly 1 K buffer—no more or no less.

•A maximum of four requests can be outstanding per stream/buffer.

•A maximum of eight requests can be outstanding per PCI segment.

In PCI-X mode:

•Each read stream requests and gets buffer in 512 B chunks.

•There is no limit on how many 512 B chunks a read stream can occupy.

•A maximum of four requests can be outstanding per stream.

•A maximum of one request can be outstanding per 512 B buffer.

•A maximum of eight requests can be outstanding per PCI-X segment.

3.2.4Configuration Transactions

Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and by the lowest two bits of the address being set to 00b.

Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration transaction is identified by the configuration command and by the lowest two bits of the address being set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the Dword address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single- function devices, this value is not decoded. Type 1 configuration transaction addresses also include a five-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.

28 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual