32 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
PCI-X Interface
3.2.7.2 PCI-X Mode Transaction Termination
•Initiator Disconnect or Satisfaction of Byte Count
As a PCI-X master, the 41210 uses normal termination (initiator disconnect or satisfaction of
byte count) if DEVSEL# is returned by the target within six clock cycles after address phase.
The 41210 terminates a transaction when one of the following conditions are met:
— Initiator disconnect occurs when all write data indicated in the byte count of the write
transaction is transferred from the 41210 data buffers to the target. The 41210 does not
perform an initiator disconnect on a write before the byte count size has been satisfied.
— Initiator disconnect at the next ADB on a split read completion because the 41210 data
buffer has run dry.
— Initiator disconnect occurs at the next ADB when the master latency timer expires and the
bus grant of the 41210 is de-asserted.
•Master Abort Termination
When a transaction initiated by the 41210 does not receive a DEVSEL# response within six
clocks after address phase, the 41210 terminates the transaction with a master abort. The
41210 sets the received master abort bit in the secondary status register. Read requests
(configuration, I/O, memory) that receive master abort termination are sent back to PCI
Express*/peer PCI with a master abort status. Delayed write requests that receive master abort
are sent back to PCI Express* with a master abort status.
Note: When the 41210 performs a Type1 to special cycle translation, a master abort is the expected
termination for the special cycle on the target bus. In this case, the master abort received bit is not
set, and the Type1 configuration transaction is disconnected after the first data phase.
•Target Abort
When the 41210 receives a target abort, and the cycle requires completion on PCI Express*,
the 41210 returns the target abort status to PCI Express*. The 41210 sets the received target
abort status bit in the secondary status register for all target aborts it receives on the PCI bus.
Target abort can happen on any data phase of a PCI-X transaction. A read com pletion packet to
PCI Express*/peer PCI that incurs a target abort in the middle of the packet returns valid data
to the point of target abort, all 1s for the reminder of the length, and a target abort completion
status for the entire packet.
•Disconnect and Retry
When the 41210 receives a disconnect response (single data phase or at next ADB) from a
target, it re-initiates the transfer with the remaining length. When the 41210 receives a retry, it
waits at least two PCI clocks before it retries the transaction. When the retried transaction is a
write, the 41210 retries the write until it completes normally or with a target or master abort.
When the retried transaction is a delayed read or delayed write transaction, the 41210 allows
memory reads, split completions, and writes to pass the transaction. Refer to Section6,
“Transaction Ordering” on page51 for details on the kinds of reordering allowed. Retry is not
considered an error condition, so there is no error logging or reporting done on a retry.
•Split Response
The 41210 can receive split response for memory reads, and I/O and configuration read and
write transactions.