Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual 53
Interrupt Support
Interrupt Support 7
The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) can
generate an in-band interrupt request on PCI Express* for boot devices and for sy st ems that do not
support Message Signaled Interrupts (MSI).

7.1 Legacy Interrupt Sharing

PCI Express* provides interrupt messages that emulate the legacy wired mechanism. This feature
allows I/O devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT
messages. This message pairing preserves the level-sensitive semantics of the PCI interrupts on
PCI Express*.
The four virtual wire interrupts (INTA–INTD) correspond to the fo ur interru pt wires defi ned in the
PCI Local Bus Specification, Revision 2.3. The 41210 routes its PCI interrupt pins and the internal
interrupts to the PCI Express* INTx interrupts as shown in Table 2 3.
Each row in Tabl e 23 indicates a logical ORing of the interrupts in that row. The
ASSERT/DEASSERT message sent out on PCI Express* capt ures the assert ing/deasserti ng edge of
the signal that represents the logical OR of the interrupts in that row.
The 41210 uses its primary bus number and device number in the Requester ID field for the PCI
Express* INTx messages. As stated in the PCI Express* Specification, Revision1.0a, the function
number is reserved for interrupt messages and is always 0.
Note: PCI Express* Assert_INTx/Deassert_INTx messages are not inhibited by the Bus Master Enable
(BME) bit.
Table 23. INTx Routing Table
A_INTx# Interrupt Pins B_INTx# Interrupt Pins PCI Express* INTx Message
A_IN TA# B_ INTA# INTA
A_INTB# B_INTB# INTB
A_INTC# B_INTC# INTC
A_INTD# B_INTD# INTD