Interrupt Support, Legacy Interrupt Sharing | Intel 41210 specs

	Interrupt Support
Interrupt Support	7

The Intel® 41210 Serial to Parallel PCI Bridge (called hereafter the 41210 Bridge or 41210) can generate an in-band interrupt request on PCI Express* for boot devices and for systems that do not support Message Signaled Interrupts (MSI).

7.1Legacy Interrupt Sharing

PCI Express* provides interrupt messages that emulate the legacy wired mechanism. This feature allows I/O devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT messages. This message pairing preserves the level-sensitive semantics of the PCI interrupts on PCI Express*.

The four virtual wire interrupts (INTA–INTD) correspond to the four interrupt wires defined in the PCI Local Bus Specification, Revision 2.3. The 41210 routes its PCI interrupt pins and the internal interrupts to the PCI Express* INTx interrupts as shown in Table 23.

Table 23.	INTx Routing Table

	A_INTx# Interrupt Pins	B_INTx# Interrupt Pins	PCI Express* INTx Message

	A_INTA#	B_INTA#	INTA

	A_INTB#	B_INTB#	INTB

	A_INTC#	B_INTC#	INTC

	A_INTD#	B_INTD#	INTD

Each row in Table 23 indicates a logical ORing of the interrupts in that row. The ASSERT/DEASSERT message sent out on PCI Express* captures the asserting/deasserting edge of the signal that represents the logical OR of the interrupts in that row.

The 41210 uses its primary bus number and device number in the Requester ID field for the PCI Express* INTx messages. As stated in the PCI Express* Specification, Revision 1.0a, the function number is reserved for interrupt messages and is always 0.

Note: PCI Express* Assert_INTx/Deassert_INTx messages are not inhibited by the Bus Master Enable (BME) bit.

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

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Intel 41210 manual Interrupt Support, Legacy Interrupt Sharing, INTx Routing Table

Contents

Developer’s Manual Intel 41210 Serial to Parallel PCI Bridge Intel 41210 Serial to Parallel PCI Bridge Developer’s Manual Contents 10.1 12.2.6 Figures Tables 118 Offset 178h PREFCTRL-Prefetch Control Register Date Revision Description Revision History Introduction1 PCI Express* Interface FeaturesPCI-X Interface Features Jtag Power ManagementSMBus Interface On-Die Termination ODT Signal Description AACK64# BACK64# AAD6332 BAD6332 ACBE#74 BCBE#74 ODT SignalsADEVSEL# BDEVSEL# AFRAME# BFRAME# AGNT#50 BGNT#50 PCI Express* Interface PCI Express* Interface PinsPERCOMP10 Total PCI Bus Interface Two Instances PCI Interface Pins Sheet 1ADEVSEL# AIRDY# PCI Interface Pins Sheet 2 PCI Bus Interface 64-Bit Extension Two Interfaces PCI Interface Pins 64-Bit ExtensionsPCI Clock and Reset Pins Interrupt Interface Two Interfaces Interrupt Interface PinsAINTA# AINTB# AINTC# AINTD# Cfgretry Reset StrapsReset Strap Pins SMBus Interface Pins Miscellaneous Pins Miscellaneous Pins Number Description Voltage Pins This page Intentionally Left Blank PCI-X Interface PCI Mode Pin/Strap EncodingInitialization PCI-X Initialization Pattern Transactions Supported PCI ModePCI Transactions Supported Transaction Encoding1 PCI-X Transactions Supported PCI-X ModeRead Transactions Delayed Configuration Transactions PCI Lock CyclesEnd Point Source Transaction Termination Decoding PCI-X Interface PCI-X Mode Transaction Termination PCI-X Interface Attributes PCI-X Protocol Specifics2 4 GB and 4 K Page Crossover Wait States Split Transactions ArbitrationFields Split Completion Abort Registers BridgeM0 High Priority Group Lpg Low Priority B3173-01 Internal Arbitration Scheme Hardware-Controlled Active State Power Management Power ManagementSoftware-Driven PCI-PM 1.1-Compatible Power Management PCI Bus Power Management Power-Management Event Signaling Pmetoack This page Intentionally Left Blank PCI-to-PCI Bridge a Configuration Space Addressable Space AccessPCI-to-PCI Bridge B Configuration Space Addressing5 PCI Express* Configuration Access Configuration-Space AccessDevice Number Signal Used for Public/Private Secondary PCI Devices Addressing Type 1 to Type 0 Translation PCI and PCI-X Type 0 Configuration Access from PCI-X Interface SMBus Configuration Access I/O Space Access Mechanism O Forwarding Memory Space Access Mechanism Memory Forwarding Memory-Mapped I/O Window Opaque Memory Window VGA AddressingPrefetchable Memory Window § § Upstream Transaction Ordering Transaction OrderingUpstream Transaction Ordering Row Pass Column Downstream Transaction Ordering Downstream Transaction OrderingRelaxed Ordering/No-Snoop Support INTx Routing Table Interrupt SupportLegacy Interrupt Sharing Interrupt Binding for Devices behind a Bridge Interrupt Routing for Devices behind a BridgeDevice Number on Secondary Bus Bit Value System Management Bus InterfaceSMBus Address Assignments SMBus Command Encoding SMBus CommandsInternal Command SMBus command SMBus Status Byte Encoding ConfigurationInitialization Sequence Clock Stretch Clock Stretch Configuration Writes Error Handling SMBus Interface Reset Local Initialization This page Intentionally Left Blank Device Reset Clock and ResetClocking Clock Domains PCI Express* Reset Mechanism PERST# Reset MechanismRSTIN# Reset Mechanism Software PCI Reset SBR-Secondary Bus Reset This page Intentionally Left Blank PCI Errors Error HandlingPCI Express* Errors Termination of Completion Required Transactions Error TypesCompletion-Status Translation for Immediate Terminations PCI-X Termination PCI Express* Completion Successful 00h PCI-X Split Termination Message PCI ExpressIndex PCI Express* Completion Status PCI Completion Split Termination on PCI Express* Interface PERST# reset Register Nomenclature and Access AttributesRegister Description Bit Attribute Definitions Configuration Registers Capptr PCI/PCI-X Compatible Configuration region0xFFF 0x300 0x100 0x40 0x00 B3174-02 Legacy Configuration Space Byte Offset PCI Express* Extended Configuration SpaceRegister Offset 04h PCICMD-Command Register Sheet 1 Offset 04h PCICMD-Command RegisterReset Description Offset 00h ID-Identifiers Offset 06h PSTS-Primary Device Status Offset 04h PCICMD-Command Register Sheet 2Offset 06h PSTS-Primary Device Status Sheet 1 Type Offset 06h PSTS-Primary Device Status Sheet 2 Offset 08h REVID-Revision IDOffset 08h REVID-Revision ID Bits Offset 09h CC-Class Code Offset 0Dh PMLT-Primary Master Latency TimerOffset 0Ch CLS-Cache-Line Size Offset 0Eh HEADTYP-Header Type Offset 1Bh SMLT-Secondary Master Latency Timer Offset 1Bh SMLT-Secondary Master Latency TimerOffset 18h BNUM-Bus Numbers Offset 18h BNUM-Bus Numbers Offset 1Ch IOBL-I/O Base and Limit Offset 1Ch IOBL-I/O Base and LimitFFFh Support for 16-bit I/O addressing only Offset 1Eh SSTS-Secondary Status Offset 1Eh SSTS-Secondary Status Offset 20h MBL-Memory Base and Limit Offset 20h MBL-Memory Base and Limit3120 000h Must be less than this value Offset 24h PMBL-Prefetchable Memory Base and Limit Bits Type Reset DescriptionOffset 28h PMBU32-Prefetchable Memory Base Upper 32 Bits Offset 24h PMBL-Prefetchable Memory Base and Limit Offset 30h IOBLU16-I/O Base and Limit Upper 16 Bits Offset 2Ch PMLU32-Prefetchable Memory Limit Upper 32 BitsOffset 34h CAPP-Capabilities List Pointer Offset 3Ch INTR-Interrupt Information Offset 3Eh BCTRL-Bridge Control Sheet 1 Offset 3Eh BCTRL-Bridge Control Offset 3Eh BCTRL-Bridge Control Sheet 2 Offset 40h BCNF-Bridge Configuration Register Offset 40h BCNF-Bridge Configuration RegisterPeer Memory Read Enable Pmre Bit Maximum Number of Upstream Delayed Transactions Offset 43h PCLKC-PCI Clock Control Offset 42h MTT-Multi-Transaction TimerOffset 44h EXPCAPID-PCI Express* Capability Identifier Offset 45h EXPNXTP-Next Item Pointer Offset 46h EXPCAP-PCI Express* Capability Default DescriptionOffset 46h EXPCAP-PCI Express* Capability Bit MaxPayloadSize Offset 4Ch EXPDCTL-PCI Express* Device Control RegisterBit MaxReadRequestSize Offset 4Eh EXPDSTS-PCI Express* Device Status Register Offset 4Eh EXPDSTS-PCI Express* Device Status RegisterOffset 50h EXPLCAP-PCI Express* Link Capabilities Register Offset 54h EXPLCTL-PCI Express* Link Control Register Bits Type Default DescriptionOffset 54h EXPLCTL-PCI Express* Link Control Register L0s Exit Latency Offset 5Dh MSINXTP-PCI Express* Next Item Pointer Offset 56h EXPLSTS-PCI Express* Link Status RegisterOffset 5Ch MSICAPID-PCI Express* MSI Capability Identifier Offset 5Eh MSIMC-PCI Express* MSI Message Control Offset 6Ch PMCAPID-Power Management Capabilities IdentifierOffset 60h MSIMA-PCI Express* MSI Message Address Offset 68h MSIMD-PCI Express* MSI Message Data Offset 6Eh PMPMC-Power Management Capabilities Offset 6Dh PMNXTP-Power Management Next Item PointerOffset 6Dh PMNXTP-Power Management Next Item Pointer Offset 6Eh PMPMC-Power Management Capabilities Offset 73h PMDATA-Power Management Data Field Offset 70h PMPMCSR-Power Management Control/Status RegisterOffset 72h PMBSE-Power Management Bridge Support Extensions Offset D9h PXNXTP-PCI-X Next Item Pointer Offset D8h PXCAPID-PCI-X Capabilities IdentifierOffset D8h PXCAPID-PCI-X Capabilities Identifier Offset D9h PXNXTP-PCI-X Next Item Pointer Offset DAh PXSSTS-PCI-X Secondary Status Offset DAh PXSSTS-PCI-X Secondary Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset DCh PXBSTS-PCI-X Bridge StatusOffset DCh PXBSTS-PCI-X Bridge Status Offset E0h PXUSTC-PCI-X Upstream Split Transaction Control Offset E4h PXDSTC-PCI-X Downstream Split Transaction Control Offset FCh BINIT-Bridge Initialization Register Offset FCh BINIT-Bridge Initialization Register Advanced Error Reporting Extended Capability Version Number Power Budgeting Capability as the next capabilityID, indicating Advanced Error Reporting Capability When the configuration unit signals a completer abort Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Offset 108h ERRUNCMSK-PCI Express* Uncorrectable Error Mask Flow Control Protocol Error Status Severity Unsupported Request Error Status SeverityData Link Protocol Error Severity Training Error Severity Not supported Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 110h ERRCORSTS-PCI Express* Correctable Error Status Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask Offset 114h ERRCORMSK-PCI Express* Correctable Error Mask 1270 Offset 11C-12Bh HDRLOG-PCI Express* Transaction Header LogOffset 11C-12Bh HDRLOG-PCI Express* Transaction Header Log Sheet 1 Logs the header Sheet 2 PCI Delayed Transaction Timer Expiry Mask Internal Bridge Data Error MaskPCI-X Uncorrectable Address Parity Error Detected Mask PCI-X Uncorrectable Attribute Parity Error Detected Mask PCI-X Detected Split Completion Master Abort Mask PCI-X Detected Target Abort Mask optional in specification PCI Delayed Transaction Timer Expiry Severity Internal Bridge Data Error SeverityPCI-X Uncorrectable Address Parity Error Detected Severity PCI-X Uncorrectable Data Parity Error Detected Severity Register is cleared by the software writing a 1 to the bit Rwcs = Errnonfatal = ErrfatalPCI-X Detected Split Completion Master Abort Severity Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Type Reset DescriptionOffset 13C-14Bh PCIXHDRLOG-Uncorrectable PCI-X Header Log Offset 16Ah ARBCNTRL-Internal Arbiter Control Register Offset 170h SSR-Strap Status Register Offset 170h SSR-Strap Status RegisterReserved Read only SMBUS5 SMBUS3 SMBUS2 SMBUS1 6360 RsvdP Offset 178h PREFCTRL-Prefetch Control RegisterOffset 178h PREFCTRL-Prefetch Control Register Offset 308h PWRBGTDATA-Power Budgeting Data Register Offset 304h PWRBGTDSEL-Power Budgeting Data Select RegisterOffset 304h PWRBGTDSEL-Power Budgeting Data Select Register Offset 308h PWRBGTDATA-Power Budgeting Data Register