Register Description

12.2.66Offset 178h: PREFCTRL—Prefetch Control Register

The following register contains prefetch parameters for PCI operation.

Table 100.

Offset 178h: PREFCTRL—Prefetch Control Register

 

 

 

 

 

 

 

Bits

 

Type

Reset

 

 

Description

 

 

 

 

 

 

63:60

 

RsvdP

0000b

Preserved

 

 

 

 

 

 

 

 

 

 

Prefetch Policy (PP): These bits control how the bridge prefetches data on behalf of PCI

 

 

 

 

masters:

 

 

 

 

 

00 =

Allow prefetching on MRM, MRL, and MR.

55:54

 

RW

01b

01 =

Allow prefetching on MRM and MRL, but not on memory read.

 

 

 

 

1x =

Disable all prefetching.

 

 

 

 

NOTE: This control applies to both inbound memory reads and peer reads to the other PCI

 

 

 

 

 

segment in the Intel® 41210 Serial to Parallel PCI Bridge.

53:22

 

RsvdP

0

Preserved

 

 

 

 

 

 

21:16

 

RW

05h

TH 66: These bits indicate the threshold parameter for 66 MHz PCI. Unit is 64B chunks and

 

is 0s based; in other words, a value of 0 in this field indicates 64B.

 

 

 

 

 

 

 

 

 

 

15:11

 

RsvdP

00h

Preserved

 

 

 

 

 

 

10:5

 

RW

03h

TH 33: These bits indicate the threshold parameter for 33 MHz PCI. Unit is 64B chunks and

 

is 0s based; in other words, a value of 0 in this field indicates 64B.

 

 

 

 

 

 

 

 

 

 

4:0

 

RsvdP

00h

Preserved

 

 

 

 

 

 

 

 

Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual

119

Page 119
Image 119
Intel 41210 manual Offset 178h PREFCTRL-Prefetch Control Register, RsvdP