Register Description
12.2.26Offset 46h: EXP_CAP—PCI Express* Capability
This register stores the version number of the capability item and other base information contained in the capability structure.
Table 60. | Offset 46h: | |||
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| Type | Default | Description |
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15:14 |
| RsvdP | 00b | Preserved |
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13:9 |
| RO | 0 0000b | Interrupt Message Number: Not relevant for the Intel® 41210 Serial to Parallel PCI Bridge |
8 |
| RO | 0b | Slot Implemented: Not relevant for the 41210 |
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7:4 |
| RO | 7h | Device/Port Type: These bits indicate that the 41210 is a PCI Express* |
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3:0 |
| RO | 1h | Version Number: These bits indicate the version number of the PCI Express* capability |
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12.2.27Offset 48h:
Register
This register stores information on the PCI Express* link capabilities.
Table 61. | Offset 48h: | |||
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Bits |
| Type | Default | Description |
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31:28 |
| RsvdP | 0h | Preserved |
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| Captured Slot Power Limit Scale: In combination with the Slot Power Limit value |
27:26 |
| RO | 00b | (bits[25:18], this field specifies the upper limit of the power supplied by slot. The power limit |
| (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power | |||
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| Limit Value field. This value is set by the Set_Slot_Power_Limit message. |
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| Captured Slot Power Limit Value: In combination with the Slot Power Limit Scale value |
25:18 |
| RO | 00h | (bits[27:26]), this field specifies the upper limit of the power supplied by slot. The power limit |
| (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power | |||
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| Limit Scale field. This value is set by the Set_Slot_Power_Limit message. |
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17:15 |
| RsvdP | 000b | Preserved |
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14 |
| RO | 0b | Power Indicator Present: Not supported |
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13 |
| RO | 0b | Attention Indicator Present: Not supported |
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12 |
| RO | 0b | Attention Button Present: Not supported |
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11:9 |
| RO | 000b | Endpoint L1 Acceptable Latency: L1 ASPM is not supported. |
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8:6 |
| RO | 000b | Endpoint L0s Acceptable Latency: The least latency possible out of L0s is supported. |
| NOTE: L0s ASPM is not supported in the 41210 Bridge. | |||
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5 |
| RO | 0b | Extended Tag Field Supported: Only a |
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4:3 |
| RO | 00b | Phantom Functions Supported: Not supported |
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2:0 |
| RO | 001b | Supported Max Payload sizes: |
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92 | Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual |
