6 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
Contents
12.2.53 Offset 108h: ERRUNC_MSK—PCI Express*
Uncorrectable Error Mask................................. ................................................... 106
12.2.54 Offset 10Ch: ERRUNC_SEV—PCI Express* Uncorrectable
Error Severity.................................................... ................................................... 107
12.2.55 Offset 110h: ERRCOR_STS—PCI Express*
Correctable Error Status.......... ............................................................................ 108
12.2.56 Offset 114h: ERRCOR_MSK—PCI Express*
Correctable Error Mask............................................................................ ............109
12.2.57 Offset 118h: ADVERR_CTL—Advanced Error Control
and Capability Register............................................................... .........................109
12.2.58 Offset 11C–12Bh: HDR_LOG—PCI Express*
Transaction Header Log ................................................................................. .....110
12.2.59 Offset 12Ch: PCIXERRUNC_STS—Uncorrectable
PCI-X Status Register........................................................... ...............................111
12.2.60 Offset 130h: PCIXERRUNC_MSK—Uncorrectable
PCI-X Error Mask Register .................................................................................. 113
12.2.61 Offset 134h: PCIXERRUNC_SEV—Uncorrectable
PCI-X Error Severity Register.................................. ............................................ 115
12.2.62 Offset 138h: PCIXERRUNC_PTR—Uncorrectable
PCI-X Error Pointer........................................... ................................................... 116
12.2.63 Offset 13C–14Bh: PCIXHDR_LOG—Uncorrectable
PCI-X Error Transaction Header Log.............................................................. .....117
12.2.64 Offset 16Ah: ARB_CNTRL—Internal Arbiter Control Regis ter... .........................117
12.2.65 Offset 170h: SSR—Strap Status Register .................................. .........................118
12.2.66 Offset 178h: PREFCTRL—Prefetch Control Register ... ......................................1 19
12.2.67 Offset 300h: PWRBGT_CAPID—Power Budge ting
Enhanced Capability Header ............................................................................... 120
12.2.68 Offset 304h: PWRBGT_DSEL—Power Budge ting
Data Select Register......................................... ................................................... 120
12.2.69 Offset 308h: PWRBGT_DATA—Power Budget ing Data Register....................... 120
Figures1 Internal Arbitration S cheme................... ..................................................................................... 36
2 Type 1 to Type 0 Translation (PCI and PCI-X) ....................................................... ....................44
3 Upstream Type 0 PCI-X Configuration Cycle Address Format .................................................. 45
4 I/O Forwarding ....................................................................... ..................................................... 46
5 Memory Forwarding ................................................................................................ ....................48
6 DWord Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled) ............. 58
7 DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) .............58
8 DWord Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled) ........... .59
9 DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled) .............59
10 DWord Configuration Write Protocol (SMBus Block Write, PEC Enabled) ................................. 60
11 DWord Configuration Write Protocol (SMBus Byte Write, PEC Enabled) .............. ....................61
12 Intel® 41210 Serial to Parallel PCI Bridge Capabilities................. .............................................. 75