62 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
System Management Bus Interface
8.4 SMBus Interface Reset
The master has two ways to reset the slave interface state machine in the 41210:
•The master holds SCLK low for 25 ms cumulative. “Cumulative” in this case means that all
the “low time” for SCLK is counted between the start and stop bit. When this count totals
25 ms before reaching the stop bit, the interface is reset.
•The master holds SCLK continuously high for 50 ms .
Besides these methods, the SMBus interface in the 41210 is also reset on a PERST#, RSTIN#, or
an in-band warm reset from P CI Express*.
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