Intel 41210 58 Intel 41210 Serial to Parallel PCI Bridge Developers Manual, Figure 7. DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled)

58 Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual
System Management Bus Interface
Figure 6. DWord Configuration Read Protocol (SMBus Block W rite/Block Read, PEC Enabled)
Figure 7. DWord Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled)
B3187-01
W Cmd = 11010010
S 11X0_XXX W A Cmd = 11010010 A Byte Count = 4 A Bus Number A A Reg Number [15:8] ADevice/Function
Reg Number [7:0] A PEC Clock Stretch AP
Sr 11X0_XXX
S 11X0_XXX
R A Byte Count = 5 A
AA
P
PEC
A Data[7:0] NA
Status A Data[31:24] A A Data[15:8]Data[23:16]
B3188-01
W Cmd = 10010001
S 11X0_XXX W A Cmd = 10010001 A
S 11X0_XXX W A Cmd = 01010001 A
Bus Number A Device/Function A A PPEC
Register Num [7:0] A Register Num [15:8] A PEC Clock Stretch AP
Sr 11X0_XXX
S 11X0_XXX
RA A
AA
Status AData[31:24] N PPEC
W Cmd = 00010001
Sr 11X0_XXX
S 11X0_XXX
RA A
AA
Data[23:16] AData[15:8] N PPEC
W Cmd = 01010000
Sr 11X0_XXX
S 11X0_XXX
RA A
AA
Data[7:0] PEC N P